The 9DB801C is a DB800 Version 2.0 Yellow Cover part with PCI Express® support. It can be used in PC or embedded systems to provide outputs that have low cycle-to-cycle jitter (50 ps), low output-to-output skew (100 ps), and are PCI Express® gen 1 compliant. The 9DB801C supports a 1 to 8 output configuration, taking a spread or non spread differential HCSL input from a CK410(B) main clock such as 954101 and 932S401, or any other differential HCSL pair. 9DB801C can generate HCSL or LVDS outputs from 50 to 200 MHz in PLL mode or 0 to 400 MHz in bypass mode. There are two de-jittering modes available selectable through the HIGH_BW# input pin, high bandwidth mode provides de-jittering for spread inputs and low bandwidth mode provides extra de-jittering for non-spread inputs. The SRC_STOP#, PD#, and individual OE# real-time input pins provide completely programmable power management control.

特長

  • 8 - 0.7 V current-mode differential output pairs
  • Supports zero delay buffer mode and fanout mode
  • Bandwidth programming available
  • Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread.
  • Supports undriven differential outputs in PD# and SRC_STOP# modes for power management.
  • Supports polarity inversion to the output enables, SRC_STOP and PD.
  • Outputs cycle-cycle jitter < 50 ps
  • Outputs skew: 50 ps
  • 50 - 200 MHz operation
  • Extended frequency range in bypass mode to 400 MHz
  • PCI Express® Gen I compliant
  • Real time PLL lock detect output pin
  • 48-pin SSOP/TSSOP package
  • Available in RoHS compliant packaging

tune製品選択

製品名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Active TSSOP 48 C はい Tube
Availability
Active TSSOP 48 C はい Reel
Availability

descriptionドキュメント

タイトル language 分類 形式 サイズ 日付
データシート
star 9DB801 Datasheet データシート PDF 175 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-843 PCI Express Reference Clock Requirements アプリケーションノート PDF 1.90 MB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PDN# : CQ-18-03 Product Discontinuance Notice 製品中止通知 PDF 218 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 544 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 95 KB
PCN# : A1506-02 Gold wire to Copper wire 製品変更通知 PDF 35 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 50 KB
PCN# : A1305-01 Gold Wire to Copper Wire 製品変更通知 PDF 148 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 製品変更通知 PDF 361 KB
PCN#: TB-0510-05 New Shipping Tube for TSSOP/TVSOP/TSSOP Exposed 製品変更通知 PDF 201 KB
その他資料
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
PCI Express Timing Solutions Overview 概要 PDF 275 KB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB

file_downloadダウンロード

タイトル language 分類 形式 サイズ 日付
モデル
9DB801 IBIS Model モデル-IBIS ZIP 15 KB