The 5X35023 is a VersaClock programmable clock generator and is designed for low power, consumer, and high performance PCI Express applications. The device is a three PLL architecture design, and each PLL is individually programmable and allowing for up to five unique frequency outputs.

The 5X35023 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshoot Reduction Technology (ORT) and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after power up, then program the 5X35023 again through the I²C interface.

The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization base on the application requirements. It also supports one single-ended output and two pair of differential outputs that support LVCMOS, LP-HCSL, LVDS, and LVPECL. A low power 32.768kHz clock is supported with only less than 2μA current consumption for system RTC reference clock.
 

特長

  • Intergrated crystal in the package for board space saving
  • Configurable OE pin function as OE, PD#, PPS or DFC control function
  • Configurable PLL bandwidth/minimizes jitter peaking
  • PPS: Proactive Power Saving features save power during the end device power down mode
  • PPB: Performance Power Balancing feature allows minimum power consumption base on required performance
  • DFC: Dynamic Frequency Control feature allows up to 4 different frequencies to switch dynamically
  • Spread spectrum clock support to lower system EMI
  • I²C interface

製品比較

5X35023 5L35021 5L35023 5P35023
Outputs (#) 5 5 7 7
Output Type LP-HCSL, LVCMOS, LVDS, LVPECL LP-HCSL, LVCMOS LP-HCSL, LVCMOS LP-HCSL, LVCMOS, LVDS, LVPECL
Core Voltage (V) 3.3 1.8 1.8 3.3
Output Voltage (V) 1.8, 2.5, 3.3 1.8 1.8 1.8, 2.5, 3.3
Pkg. Dimensions (mm) 4.0 x 4.0 x 1.5 3.0 x 3.0 x 1.0 4.0 x 4.0 x 0.9 4.0 x 4.0 x 0.9

descriptionドキュメント

タイトル language 分類 形式 サイズ 日付
star 5X35023 Datasheet データシート PDF 647 KB
Timing Commander Installation Guide ガイド PDF 497 KB
VersaClock 3S – 5x3502x Family Development Kit User Manual マニュアル-ハードウェア PDF 723 KB
Timing Commander Software for VersaClock 3S - 5P3502x マニュアル-ソフトウェア PDF 1.65 MB
How to Make 1.2V LVCMOS from 1.8V LVCMOS Output アプリケーションノート PDF 256 KB
AN-954 Layout and EMI Recommendations for Automotive Applications アプリケーションノート PDF 406 KB
AN-960 Layout and EMI Recommendations for Automotive Applications (short form) アプリケーションノート PDF 342 KB
AN-909 PCB Layout Considerations for Designing IDT VersaClock 3S, 5 and 6 Clock Products アプリケーションノート PDF 901 KB
AN-918 Programmable Clocks vs Crystal Oscillators アプリケーションノート PDF 307 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs アプリケーションノート PDF 480 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-846 Termination - LVDS アプリケーションノート PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-806 Power Supply Noise Rejection アプリケーションノート PDF 438 KB
AN-808 PCI Express/HCSL Termination アプリケーションノート PDF 137 KB
PCN# : TP1910-01 VBAT Power Domain Required 製品変更通知 PDF 110 KB
VersaClock Family Overview 概要 PDF 376 KB
IDT Clock Generation Overview 概要 PDF 1.83 MB
5X35023 Reference Schematic 回路図 PDF 53 KB
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs 技術概要 PDF 238 KB

file_downloadダウンロード

タイトル language 分類 形式 サイズ 日付
Timing Commander Installer (v1.17) ソフトウェア/ツール-その他 ZIP 18.02 MB
VersaClock 3S Timing Commander Personality File ソフトウェア/ツール-その他 ZIP 5.80 MB

memoryボード&キット

製品名 タイトル 分類 会社名
DEV5P35023 5P35023 and 5X35023 VersaClock 3S Programmable Clock Development Kit Development Renesas