The 9ZX21901D is a second generation DB1900Z differential buffer for Intel Purley and newer platforms. The part is backwards compatible to the 9ZX21901C while offering much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications. In bypass mode, the 9ZX21901D can provide outputs up to 400MHz. 

特性

  • 19 HCSL output pairs
  • Fixed feedback path
  • Phase jitter: PCIe Gen4 < 0.5ps rms
  • Phase jitter: UPI 9.6GT/s < 0.1ps rms
  • PLL or bypass mode; PLL can dejitter incoming clock
  • 9 selectable SMBus Addresses
  • 8 dedicated OE# pins
  • 100MHz or 133MHz PLL mode; legacy QPI support
  • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
  • Spread spectrum compatible
  • SMBus interface
  • 10 × 10 mm 72-QFN package

产品选择

下单器件型号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 72 C 是的 Tray
Availability
Active VFQFPN 72 C 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
9ZX21901D Datasheet 数据手册 PDF 307 KB
应用指南 &白皮书
AN-975 Cascading PLLs 应用文档 PDF 255 KB
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-808 PCI Express/HCSL Termination 应用文档 PDF 137 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
下载
9ZX21901D IBIS Model 模型 - IBIS ZIP 12 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
PCI Express Timing Solutions Overview 概览 PDF 275 KB
9ZX21901 Reference Schematic 原理图 PDF 25 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB