The 9DBL0653 Zero-Delay/Fanout buffer is a low-power high-performance member of Reneas' Full-Featured PCIe family. The buffer supports PCIe Gen1–5 and provides a Loss of Signal (LOS) indicator. The device is an easy upgrade from the 9DBL0651.
 
For information regarding evaluation boards and material, please contact your local sales representative.
 

特性

  • Loss of Signal (LOS) output; supports fault tolerant systems
  • Supports PCIe Gen1–5 CC and IR in fanout mode
  • Supports PCIe Gen1–5 CC in High Bandwidth ZDB mode
  • Direct connection to 85Ω transmission lines; saves 24 resistors compared to standard PCIe devices
  • Spread spectrum tolerant; allows reduction of EMI
  • Pin/SMBus selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
  • Easy AC-coupling to other logic families, see application note AN-891.
  • Space saving 5 × 5 mm 40-VFQFPN; minimal board space

tune产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Output Impedance Carrier Type Buy Sample
Active VFQFPN 40 I 85 Tray
Availability
Active VFQFPN 40 I 85 Reel
Availability

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star 9DBL02x3-04x3-06x3-08x3 Family Datasheet 数据手册 PDF 473 KB
使用指南与说明
Timing Products for NXP (Freescale) i.MX (Chinese) English 指南 PDF 512 KB
应用指南 & 白皮书
AN-975 Cascading PLLs 应用文档 PDF 255 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs 应用文档 PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL 应用文档 PDF 235 KB
AN-843 PCI Express Reference Clock Requirements 应用文档 PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
其他
PCI Express Timing Solutions Overview 概览 PDF 275 KB
9DBL06xx Reference Schematic 原理图 PDF 118 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB

file_download下载

文档标题 language 类型 文档格式 文件大小 日期
模型
9DBL06P1 IBIS Model 模型 - IBIS ZIP 118 KB