The IDT9112-17 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz.
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Pkg. Type |
Lead Count (#) |
Temp. Grade |
Pb (Lead) Free |
Carrier Type |
购买 / 样片 |
|
---|---|---|---|---|---|---|
器件号 | ||||||
QSOP | 16 | C | Yes | Tube | ||
QSOP | 16 | C | Yes | Reel | ||
SOIC | 16 | C | Yes | Tube | ||
SOIC | 16 | C | Yes | Reel | ||
QSOP | 16 | C | Yes | Tube | ||
QSOP | 16 | C | Yes | Reel | ||
SOIC | 16 | C | Yes | Tube | ||
SOIC | 16 | C | Yes | Reel |