Features
- Low-Power HCSL outputs with Zo = 85Ω; save power and board space - no termination resistors required. Ideal for blade servers
- Space-saving 40-pin VFQFPN package
- Fixed feedback path for 0ps input-to-output delay
- 6 OE# pins; hardware control of each output
- PLL or bypass mode; PLL can de-jitter incoming clock
- Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
- Spread spectrum compatible; tracks spreading input clock for low EMI
- Cycle-to-Cycle jitter < 50ps
- Output-to-Output skew < 65ps
- Input-to-Output delay variation < 50ps
- PCIe Gen 3 phase jitter < 1.0ps RMS
- QPI/UPI 9.6GT/s 12UI phase jitter < 0.2ps RMS
Description
The 9ZXL0651 is a low-power 6-output differential buffer that meets all the performance requirements of the Intel DB1200Z specification. It consumes 50% less power than standard HCSL devices and has internal terminations to allow direct connection to 85Ω transmission lines. It is suitable for PCI Express Gen 1/2/3 or QPI/UPI applications and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications.
Parameters
| Attributes | Value |
|---|---|
| Chipset Manufacturer | Intel |
| Clock Spec. | DB800ZL v1.1 Derivative |
| Diff. Outputs | 6 |
| Diff. Output Signaling | LP-HCSL |
| Output Enable (OE) Pins | 6 |
| Output Freq Range (MHz) | 25 - 150 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 445 |
| Advanced Features | HW PLL mode control |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, QPI |
| Package Area (mm²) | 25 |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.9 | 40 | 0.4 |
Applications
- Buffer for Romley, Grantley and Purley Servers, SSDs, and PCIe