The 8T73S208 is a high-performance differential LVPECL clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 8T73S208 is characterized to operate from a 2.5V and 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8T73S208 ideal for those clock distribution applications demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the reference source easy and reduce passive component count. Each output can be individually enabled or disabled in the high-impedance state controlled by a I2C register. On power-up, all outputs are enabled. 

特性

  • One differential input reference clock
  • Differential pair can accept the following differential input levels: LVDS, LVPECL, CML
  • Integrated input termination resistors
  • Eight LVPECL outputs
  • Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
  • Maximum input clock frequency: 1000MHz
  • LVCMOS interface levels for the control inputs
  • Individual output enable/disabled by I2C interface
  • Output skew: <60ps
  • Output rise/fall times: 350ps (maximum)
  • Low additive phase jitter, RMS: 0.182ps (typical)
  • Full 2.5V and 3.3V supply voltages
  • Available in Lead-free (RoHS 6) 32-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8T73S208BNLGI
Active VFQFPN 32 I 是的 Tray
Availability
8T73S208BNLGI8
Active VFQFPN 32 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
Errata# : NEN-16-01 Datasheet Errata for 8T73S208BNLGI, 8T73S208BNLGI8 数据手册勘误表 PDF 64 KB
8T73S208 Datasheet 数据手册 PDF 730 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 产品变更通告 PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 544 KB
PCN# : A1403-03 Gold wire to Copper wire 产品变更通告 PDF 42 KB
下载
8T73S208I IBIS Model 模型 - IBIS ZIP 86 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB