The 8T73S1802 is a fully integrated clock fanout buffer and frequency divider. The input signal is frequency-divided and then fanned out to one differential LVPECL and one LVCMOS output. Each of the outputs can select its individual divider value from the range of ÷1, ÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and SEL1 (3-level logic) are available to select the frequency dividers and the output enable/disable state. The single-ended LVCMOS output is phase-delayed by 650ps to minimize coupling of LVCMOS switching into the differential output during its signal transition.

The 8T73S1802 is optimized to deliver very low phase noise clocks. The VBB output generates a common-mode voltage reference for the differential clock input so that connecting the VBB pin to an unused input (nCLK) enables to use of single-ended input signals. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. The 8T73S1802 can be used with a 3.3V or a 2.5V power supply. The device is a member of the high-performance clock family from IDT.

特性

  • High-performance fanout buffer clock and fanout buffer
  • Input clock signal is distributed to one LVPECL and one LVCMOS output
  • Configurable output dividers for both LVPECL and LVCMOS outputs
  • Supports clock frequencies up to 1000MHz (LVPECL) and up to 200MHz (LVCMOS)
  • Flexible differential input supports LVPECL, LVDS and CML
  • VBB generator output supports single-ended input signal applications
  • Optimized for low phase noise
  • 650ps delay between LVCMOS and LVPECL minimizes coupling between outputs
  • Supply voltage: 3.3V or 2.5V
  • -40°C to 85°C ambient operating temperature
  • 16 VFQFN package (3mm x 3mm)

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8T73S1802NLGI
Active VFQFPN 16 I 是的 Tray
Availability
8T73S1802NLGI/W
Active VFQFPN 16 I 是的 Reel
Availability
8T73S1802NLGI8
Active VFQFPN 16 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
8T73S1802 Datasheet 数据手册 PDF 1.04 MB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : PCN200016 Change Shipping Media on Select Package 产品变更通告 PDF 2.97 MB
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel
产品变更通告 PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel
产品变更通告 PDF 5.61 MB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
PCN# : A1809-04 Add Alternate Assembly Location for QFN packages 产品变更通告 PDF 36 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 544 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB