The 9DB403 is compatible with the Intel DB400v2 Differential Buffer Specification. This buffer provides 4 PCI Express® Gen2 clocks. The 9DB403 is driven by a differential output pair from a CK410B+, CK505 or CK509B main clock generator.

特性

  • 4 - 0.7 V current-mode differential output pairs
  • Supports zero delay buffer mode and fanout mode
  • Bandwidth programming available
  • 50-100 MHz operation in PLL mode
  • 50-400 MHz operation in Bypass mode
  • Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread.
  • Supports undriven differential outputs in PD# and SRC_STOP# modes for power management.
  • Outputs cycle-cycle jitter < 50 ps
  • Outputs skew: 50 ps
  • Phase jitter: PCIe Gen1 < 86 ps peak to peak
  • Phase jitter: PCIe Gen2 < 3.0/3.1 ps rms
  • 28-pin SSOP/TSSOP pacakge
  • Available in RoHS compliant packaging
  • Supports Commercial (0 to +70°C) and Industrial (-40 to +85°C) temperature ranges

产品选择

下单器件型号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9DB403DFILF
Active SSOP 28 I 是的 Tube
Availability
9DB403DFILFT
Active SSOP 28 I 是的 Reel
Availability
9DB403DFLF
Active SSOP 28 C 是的 Tube
Availability
9DB403DFLFT
Active SSOP 28 C 是的 Reel
Availability
9DB403DGILF
Active TSSOP 28 I 是的 Tube
Availability
9DB403DGILFT
Active TSSOP 28 I 是的 Reel
Availability
9DB403DGLF
Active TSSOP 28 C 是的 Tube
Availability
9DB403DGLFT
Active TSSOP 28 C 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
9DB403D Datasheet 数据手册 PDF 241 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-843 PCI Express Reference Clock Requirements 应用文档 PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
PCI Express Timing Solutions Overview 概览 PDF 275 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB