概览

描述

The 9FGV0441 is an 4-output very low power clock generator for PCIe Gen1–4 applications with integrated output terminations providing Zo = 100Ω. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

特性

  • Integrated terminations provide 100Ω differential Zo; reduced component count and board space
  • 1.8V operation; reduced power consumption
  • OE# pins; support DIF power management
  • LP-HCSL differential clock outputs; reduced power and board space
  • Programmable slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • DIF outputs blocked until PLL is locked; clean system start-up
  • Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
  • External 25MHz crystal; supports tight ppm with 0 ppm synthesis error
  • Configuration can be accomplished with strapping pins; SMBus interface not required for device control
  • 3.3V tolerant SMBus interface works with legacy controllers
  • Space saving 5 x 5 mm 32-VFQFPN; minimal board space
  • Selectable SMBus addresses; multiple devices can easily share an SMBus segment

应用

文档

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指南
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概览
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设计和开发

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支持