Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

特性

  • 28-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSGEN and RESET inputs
  • Low voltage operation: VDD = 1.7V to 1.9V

description文档

文档标题 language 类型 文档格式 文件大小 日期
star 74SSTUBF32868A Data Sheet 数据手册 PDF 723 KB
PCN#: A1309-03 Additional Assembly Sources 产品变更通告 PDF 398 KB