The 8A34044 Multichannel Digital PLL / Digitally Controlled Oscillator (DPLL/DCO) provides tools to manage timing references, clock conversion and timing paths for common communications protocols such as: Synchronous Ethernet (SyncE), Optical Transport Network (OTN) and Common Public Radio Interface (CPRI).  The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for: clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.


  • Two independent Digital PLLs (DPLLs)
  • Six independent Digitally Controlled Oscillators (DCOs)
  • Jitter output below 150fs RMS (typical)
  • DPLLs lock to any frequency from 1kHz to 1GHz
  • DPLLs / DCOs generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • Supports up to 2 differential or 4 single-ended reference clock inputs
  • Supports up to 12 differential outputs or 24 LVCMOS outputs
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • Optional XO_DPLL input allows a wider range for XO, TCXO or OCXO frequencies from 1MHz to 150MHz for applications that require a local oscillator with high stability
  • Serial processor ports support 1MHz I2C or 50MHz SPI
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory 
    • Standard external I2C EPROM via separate I2C Master Port


下单器件型号 Part Status Temp. Range Carrier Type Buy Sample
Active -40 to 85°C Reel
Active -40 to 85°C Reel
Active -40 to 85°C Tray


文档标题 其他语言 类型 文档格式 文件大小 日期
8A3xxxx Firmware Version v4.8.7 Errata Notice 勘误表 PDF 38 KB
8A34044 Datasheet 数据手册 PDF 2.16 MB
8A3xxxx Family Errata (Rev B with Update v4.7) 勘误表 PDF 127 KB
8A3xxxx Firmware Version v4.8.7 Release Notes 指南 PDF 143 KB
8A3xxxx Family Programming Guide (v4.8.7) 指南 PDF 2.33 MB
8A3xxxx Family Programming Guide (v4.8) 指南 PDF 3.60 MB
8A34xxx 72QFN EVK User Manual 手册 - 评估板 PDF 2.03 MB
ClockMatrix GUI Step-by-Step User Guide 指南 PDF 4.98 MB
应用指南 &白皮书
Aligning 1PPS Clocks in Larger Chassis Systems 应用文档 PDF 1.62 MB
AN-807 Recommended Crystal Oscillators for Network Synchronization 应用文档 PDF 148 KB
AN-1010 ClockMatrix Time-to-Digital Converter 应用文档 PDF 1.57 MB
Mapping Clock Device Pins to Clock Numbers in the 8A34001 应用文档 PDF 390 KB
Translating Non-Integer Frequencies with ClockMatrix 应用文档 PDF 880 KB
Auto-Alignment of Outputs 应用文档 PDF 584 KB
Locking a ClockMatrix DPLL to Internal Feedback 应用文档 PDF 155 KB
AN-1030 CM Input/Input-to-Output/Output Phase Adjustment 应用文档 PDF 976 KB
AN-1020 ClockMatrix on nCXO Redundancy 应用文档 PDF 659 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment 应用文档 PDF 324 KB
PCN# : TP2002-01 Firmware Update from v4.8 to v4.8.7 产品变更通告 PDF 301 KB
PCN# : TP1906-05 Correct System APLL Loss-of-Lock Issue 产品变更通告 PDF 123 KB
PCN#: TP1902-02 ROM Update for ClockMatrix Products 产品变更通告 PDF 435 KB
Timing Commander Installer (v1.16.3) 软件 ZIP 19.85 MB
Timing Commander Personality File for ClockMatrix 8A340xx (v8.4.1, FWv4.8.7) 软件 TCP 46.94 MB
ClockMatrix Register Header Files v4.8.7 软件 ZIP 278 KB
8A340xx ClockMatrix IBIS Model 模型 - IBIS ZIP 2.40 MB
8A34044 BSDL Model 模型 - BSDL ZIP 2 KB
EEPROM_Image_PR4.7_Part=24xx1025_Address=0x50-0x54 软件 ZIP 177 KB
EEPROM_Image_PR4.7_Part=24xx1024_Address=0x50-0x51 软件 ZIP 177 KB
8A3x0xx Schematic Checklist (v1.23) 其它参数 XLSX 318 KB
ClockMatrix Family Overview 概览 PDF 241 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
ClockMatrix 72-QFN (12 Output) Reference Schematic 原理图 PDF 98 KB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB

Boards & Kits

器件号 文档标题 类型 公司
8A34044-EVK Evaluation Kit for 8A34044 ClockMatrix