The MX0141V is comprised of a high-speed 1:4 multiplexer (mux) path and a low-speed 1:4 mux path.

The high-speed path is a bidirectional 12-bit port 1:4 mux. The low-speed path is a unidirectional 4-bit port 1:4 mux. Both high-speed and low-speed paths support SSTL_12 and SSTL_18 signaling.

Both paths are controlled in an identical manner using the input control signals: SEL1, SEL0, and EN_B. For example, when EN_B is asserted LOW, one of the high-speed [ABCD] ports is connected to IN while all the remaining ports are tri-stated. When input EN_B is HIGH all four [ABCD] ports are tri-stated.


  • 1:4 mux (separate high-speed and low-speed groups)
  • SSTL18 and SSTL12 signaling through mux
  • Mux RON = 8Ω at 0.9V condition
  • 533MT/s high speed 12-bit ports, 50MT/s low speed 4-bit ports
  • Bidirectional ports
  • Pin-to-pin output skew < 50ps
  • Propagation delay < 100ps
  • Insertion loss < 2dB


器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Carrier Type Buy Sample
Active FCCSP 98 C Tray
Active FCCSP 98 C Reel


文档标题 language 类型 文档格式 文件大小 日期
MX0141VA0 Advance Datasheet Datasheet - Advance PDF 262 KB
MX0141VA0 Advance Short-Form Datasheet 简易格式数据手册 PDF 199 KB
Memory Multiplexer Family Overview 概览 PDF 807 KB