NOTICE - The following device(s) are recommended alternatives:

The 845254I is a 3.3V/2.5V CML clock generator designed for Ethernet applications. The device synthesizes either a 50MHz, 62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz or 312.5MHz clock signal with excellent phase jitter performance. The clock signal is distributed to four low-skew differential CML outputs. The device is suitable for driving the reference clocks of Ethernet PHYs. The device supports 3.3V and 2.5V voltage supply and is packaged in a small, lead-free (RoHS 6) 32-lead VFQFN package. The extended temperature range supports telecommunication, wireless infrastructure and networking end equipment requirements.

特性

  • Clock generation of: 50MHz, 62.5MHz, 100MHz, 125MHz, 156.25MHz, 250MHz and 312.5MHz
  • Four differential CML clock output pairs
  • 25MHz reference clock (selectable internal crystal oscillator and external LVCMOS clock)
  • RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz – 20MHz): 0.405ps (typical)

    Offset                      Noise Power
      100Hz.................... -104.6 dBc/Hz
        1kHz.................... -118.4 dBc/Hz
      10kHz................... -124.1 dBc/Hz
    100kHz................... -125.3 dBc/Hz
     
  • LVCMOS interface levels for the control inputs
  • Full 3.3V and 2.5V supply voltage
  • Available in lead-free (RoHS 6) 32 VFQFN package
  • -40°C to 85°C ambient operating temperature

tune产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete VFQFPN 32 I 是的 Tray
Availability
Obsolete VFQFPN 32 I 是的 Reel
Availability

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star 845254 Datasheet 数据手册 PDF 449 KB
应用指南 & 白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-837 Overdriving the Crystal Interface 应用文档 PDF 133 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products 应用文档 PDF 108 KB
PCN / PDN
PDN# : CQ-15-04 Quarterly Market Declined PDN 产品停产通告 PDF 545 KB
其他
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB

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