NOTICE - The following device(s) are recommended alternatives:

The 83210 is a low skew, 1-to-10 HSTL Fanout Buffer. The class II HSTL outputs are balanced push-pull in design, capable of delivering 16mA into a 10pF load. This class allows both source series termination and symmetrically double parallel termination.

特性

  • Ten single-ended HSTL outputs
  • One single-ended HSTL clock input
  • Maximum input frequency: 150MHz
  • Output skew: 110ps (maximum)
  • Part-to-part skew: 2ns (maximum)
  • 1.5V power supply
  • 0°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
83210AYLF
Obsolete TQFP 32 C 是的 Tray
Availability
83210AYLFT
Obsolete TQFP 32 C 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
83210 Datasheet 数据手册 PDF 187 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : CQ-19-01(R1) Quarterly Market Declined PDN 产品停产通告 PDF 1014 KB
PDN# : CQ-19-01 Quarterly Market Declined PDN 产品停产通告 PDF 537 KB
PCN# : A1402-02 Alternate Assembly Locations 产品变更通告 PDF 34 KB
下载
83210 IBIS Model 模型 - IBIS ZIP 42 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Fanout Buffers Product Overview 产品简述 PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief 产品简述 PDF 378 KB