Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

特性

  • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSR and RESET inputs
  • Low voltage operation VDD = 1.7V to 1.9V

tune产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active CABGA 96 C 是的 Tray
Availability
Active CABGA 96 C 是的 Reel
Availability

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star 74SSTUBF32866B Datasheet 数据手册 PDF 710 KB
PCN / PDN
PCN# : PCN20001 Add Alternate Substrate Supplier for Select CABGA and FCBGA Packages 产品变更通告 PDF 113 KB
PCN# : A1609-02 Alternate Site at OSET Taiwan on Select Packages 产品变更通告 PDF 30 KB
PCN#: A1309-03 Additional Assembly Sources 产品变更通告 PDF 398 KB