CubeSuite+ Device Information for RL78, 78K
The product name of CubeSuite+, an integrated development environment from Renesas, has been changed to "CS+" from V. 3.00.00, which was released on October 1, 2014.
CubeSuite+ Device Information for RL78, 78K is divided into CS+ Device Information for RL78 and CS+ Device Information for 78K
for supporting CS+ V3.00.00.
For details about changes of V3.00.00 and later, refer to the following URL:
- CS+ Device Information for RL78
https://www.renesas.com/cs+/eng/CSPlus_DevInfo_RL78.html
- CS+ Device Information for 78K
https://www.renesas.com/cs+/eng/CSPlus_DevInfo_78K.html
Changes from V1.00.17 to V1.00.18 (Jul. 16, 2014)
1. Supported Devices Increased
- RL78/G14 group
[Target devices]
R5F104PL, R5F104PK, R5F104ML, R5F104MK,
R5F104LL, R5F104LK, R5F104JL, R5F104JK,
R5F104GL, and R5F104GK
2. Addition of Pin Configuration Information
[Target devices]
RL78/F13 group
RL78/F14 group
RL78/G10 group
Changes from V1.00.15 to V1.00.17 (Mar. 24, 2014)
1. Supported Devices Increased
- RL78/G10 group
[Target devices]
R5F10Y17, R5F10Y44, R5F10Y46, R5F10Y47
- RL78/L1C group
[Target devices]
R5F110NE, R5F111NE, R5F110NF, R5F111NF
R5F110NG, R5F111NG, R5F110NH, R5F111NH
R5F110NJ, R5F111NJ
2. Addition and Modification of SFR Information
- RL78/L1C group
[Target devices]
R5F110ME, R5F110MF, R5F110MG, R5F110MH
R5F110MJ, R5F110PE, R5F110PF, R5F110PG
R5F110PH, R5F110PJ
R5F111ME, R5F111MF, R5F111MG, R5F111MH
R5F111MJ, R5F111PE, R5F111PF, R5F111PG
R5F111PH, R5F111PJ
R5F110NE, R5F111NE, R5F110NF, R5F111NF
R5F110NG, R5F111NG, R5F110NH, R5F111NH
R5F110NJ, R5F111NJ
[Contents]
(1)The following BIT registers have been deleted:
LCDIF0 (Address:FFFD0h bit5),
LCDMK0 (Address:FFFD4h bit5),
LCDPR00 (Address:FFFD8h bit5),
LCDPR10 (Address:FFFDCh bit5)
(2)The following registers have been added.
- UCKSEL (Address:FF06C4h) (Products with USB only)
- HIOTRM (Address:FF00A0h)
(3)The following register has been deleted.
- MLCD (Address:FFF4Ch)
(4)The interrupt request name of the vector table address has been deleted.
- INTLCD0 (Address:004Eh)
3. Problem Fixed
The following problem has been fixed:
- Problem with an on-chip debug option byte value is neither specified as the link options setting for the CA78K0R compiler
nor in an assembler source file
For details of the problem, see RENESAS TOOL NEWS Document No. 140316/tn2
https://www.renesas.com/document/tnn/note-using-device-information-rl78-family-managed-cubesuite
Changes from V1.00.14 to V1.00.15 (Sep. 30, 2013)
1. Supported Devices Increased
- RL78/F13 group
[Target devices]
R5F10A6A, R5F10A6C, R5F10A6D, R5F10A6E
R5F10AAA, R5F10AAC, R5F10AAE, R5F10ABA
R5F10ABC, R5F10ABD, R5F10ABE, R5F10AGA
R5F10AGC, R5F10AGD, R5F10AGE, R5F10ALC
R5F10ALD, R5F10ALE
2. Modification of SFR Information
- RL78/F13 group
[Target devices]
R5F10AGF, R5F10AGG, R5F10ALF, R5F10ALG,
R5F10AME, R5F10AMF, R5F10AMG
R5F10BAC, R5F10BAD, R5F10BAE, R5F10BAF,
R5F10BAG, R5F10BBC, R5F10BBD, R5F10BBE,
R5F10BBF, R5F10BBG, R5F10BGC, R5F10BGD,
R5F10BGE, R5F10BGF, R5F10BGG, R5F10BLC,
R5F10BLD, R5F10BLE, R5F10BLF, R5F10BLG,
R5F10BME, R5F10BMF, R5F10BMG
[Contents]
(1)The following register name has been deleted.
- TRDELC
3. Modification of Debug Information
- RL78/I1A group
[Contents]
The wide voltage mode information used by the debugger has been modified.
Changes from V1.00.12 to V1.00.14 (Aug. 1, 2013)
1. Supported Devices Increased
- RL78/L1C group
- RL78/F14 group
[Target devices]
R5F10PGG, R5F10PGH, R5F10PGJ, R5F10PLG,
R5F10PLH, R5F10PLJ, R5F10PMG, R5F10PMH,
R5F10PMJ, R5F10PPE, R5F10PPF, R5F10PPG,
R5F10PPH
2. Deletion for the following devices
- 78K0 uPD78F8039
[Target devices]
uPD78F8033, uPD78F8034, uPD78F8035, uPD78F8036
uPD78F8037, uPD78F8039
3. Modification and Addition of SFR Information
- RL78/F13 group
[Target devices]
R5F10AGF, R5F10AGG, R5F10ALF, R5F10ALG
R5F10AME, R5F10AMF, R5F10AMG
[Contents]
(1)The following register names have been added.
NFEN2/ SSR10/ SSR10L/ SSR11/ SSR11L/ SIR10/ SIR10L/
SIR11/ SIR11L/ SMR10/ SMR11/ SCR10/
SCR11/ SE1/ SE1L/ SS1/ SS1L/ ST1/
ST1L/ SPS1/ SPS1L/ SO1/ SOE1/ SOE1L/
EDR10/ EDR11/ SOL1/ SOL1L/ SSE1/ SSE1L/ TCR10/
TCR11/ TCR12/ TCR13/ TMR10/ TMR11/ TMR12/
TMR13/ TSR10/ TSR10L/ TSR11/ TSR11L/ TSR12/
TSR12L/ TSR13/ TSR13L/ TE1/ TE1L/ TS1/ TS1L/ TT1/ TT1L/
TPS1/ TO1/ TO1L/ TOE1/ TOE1L /TOL1/ TOL1L/ TOM1/ TOM1L/ PWMDLY2/ IICCTL00/
IICCTL01/ IICWL0/ IICWH0/ SVA0/ SDR10/ SDR10L/ SDR11/ SDR11L/ IICA0/
IICS0/ IICF0/ TDR10/ TDR11/ TDR11L/ TDR11H/ TDR12/ TDR13/ TDR13L/ TDR13H/
PIOR2(80-pin products only)/ PIOR3(80-pin products only)
(2)The following attribute of register of bit1 have been changed from Read only to Read/Write.
bit 3 of NFEN0 register
bit 1,3,4 of PER0 register
bit 0,1 of PSRSEL register
bit 2,3 of DTCEN1 register
bit 0,1,2,3 of DTCEN4 register
bit 3,4,5,6 of IF2H register
bit 3,4,5,6 of MK2H register
bit 3,4,5,6 of PR02H register
bit 3,4,5,6 of PR12H register
bit 2 of IF1L register
bit 5,6 of IF1H register
bit 2 of MK1L register
bit 5,6 of MK1H register
bit 2 of PR01L register
bit 5,6 of PR01H register
bit 2 of PR11L register
bit 5,6 of PR11H register
bit 0,1 of EGP1 register(48-pin products only)
bit 0,1,2 of EGP1 register(64-pin products only)
bit 0,1 of EGN1 register(48-pin products only)
bit 0,1,2 of EGN1 register(64-pin products only)
(3)The following bit symbol names have been added.
TAU1EN(bit 1 of PER0 register)
SAU1EN(bit 3 of PER0 register)
IICA0EN(bit 4 of PER0 register)
SPT0(bit 0 of IICCTL00 register)
STT0(bit 1 of IICCTL00 register)
ACKE0(bit 2 of IICCTL00 register)
WTIM0(bit 3 of IICCTL00 register)
SPIE0(bit 4 of IICCTL00 register)
WREL0(bit 5 of IICCTL00 register)
LREL0(bit 6 of IICCTL00 register)
IICE0(bit 7 of IICCTL00 register)
PRS0(bit 0 of IICCTL01 register)
DFC0(bit 2 of IICCTL01 register)
SMC0(bit 3 of IICCTL01 register)
DAD0(bit 4 of IICCTL01 register)
CLD0(bit 5 of IICCTL01 register)
WUP0(bit 7 of IICCTL01 register)
DTCEN12(bit 2 of DTCEN1 register)
DTCEN13(bit 3 of DTCEN1 register)
DTCEN40(bit 0 of DTCEN4 register)
DTCEN41(bit 1 of DTCEN4 register)
DTCEN42(bit 2 of DTCEN4 register)
DTCEN43(bit 3 of DTCEN4 register)
SPD0(bit 0 of IICS0 register)
STD0(bit 1 of IICS0 register)
ACKD0(bit 2 of IICS0 register)
TRC0(bit 3 of IICS0 register)
COI0(bit 4 of IICS0 register)
EXC0(bit 5 of IICS0 register)
ALD0(bit 6 of IICS0 register)
MSTS0(bit 7 of IICS0 register)
IICRSV0(bit 0 of IICF0 register)
STCEN0(bit 1 of IICF0 register)
IICBSY0(bit 6 of IICF0 register)
STCF0(bit 7 of IICF0 register)
PIF11(bit 7 of IF2L register) (64-pin products only)
TMIF10(bit 3 of IF2H register)
TMIF11(bit 4 of IF2H register)
TMIF12(bit 5 of IF2H register)
TMIF13(bit 6 of IF2H register)
PMK11(bit 3 of MK2L register) (64-pin products only)
TMMK10(bit 3 of MK2H register)
TMMK11(bit 4 of MK2H register)
TMMK12(bit 5 of MK2H register)
TMMK13(bit 6 of MK2H register)
PPR011(bit 3 of PR02L register) (64-pin products only)
TMPR010(bit 3 of PR02H register)
TMPR011(bit 4 of PR02H register)
TMPR012(bit 5 of PR02H register)
TMPR013(bit 6 of PR02H register)
PPR111(bit 3 of PR12L register) (64-pin products only)
TMPR110(bit 3 of PR12H register)
TMPR111(bit 4 of PR12H register)
TMPR112(bit 5 of PR12H register)
TMPR113(bit 6 of PR12H register)
IICAIF0(bit 2 of IF1L register)
PIF8(bit 3 of IF1L register) (48 and 64-pin products only)
TMIF11H(bit 1 of IF1H register)
TMIF13H(bit 2 of IF1H register)
PIF9(bit 3 of IF1H register) (48 and 64-pin products only)
PIF10(bit 4 of IF1H register) (64-pin products only)
STIF1/ CSIIF10/ IICIF10(bit 5 of IF1H register)
SRIF1/ CSIIF11/ IICIF11(bit 6 of IF1H register)
IICAMK0(bit 2 of MK1L register)
PMK8(bit 3 of MK1L register) (48 and 64-pin products only)
TMMK11H(bit 1 of MK1H register)
TMMK13H(bit 2 of MK1H register)
PMK9(bit 3 of MK1H register) (48 and 64-pin products only)
PMK10(bit 4 of MK1H register) (64-pin products only)
STMK1/ CSIMK10/ IICMK10(bit 5 of MK1H register)
SRMK1/ CSIMK11/ IICMK11(bit 6 of MK1H register)
IICAPR00(bit 2 of PR01L register)
PPR08(bit 3 of PR01L register) (48 and 64-pin products only)
TMPR011H(bit 1 of PR01H register)
TMPR013H(bit 2 of PR01H register)
PPR09(bit 3 of PR01H register) (48 and 64-pin products only)
PPR010(bit 4 of PR01H register) (64-pin products only)
STPR01/ CSIPR010/ IICPR010(bit 5 of PR01H register)
SRPR01/ CSIPR011/ IICPR011(bit 6 of PR01H register)
IICAPR10(bit 2 of PR11L register)
PPR18(bit 3 of PR11L register) (48 and 64-pin products only)
TMPR111H(bit 1 of PR11H register)
TMPR113H(bit 2 of PR11H register)
PPR19(bit 3 of PR11H register) (48 and 64-pin products only)
PPR110(bit 4 of PR11H register) (64-pin products only)
STPR11/ CSIPR110/ IICPR110(bit 5 of PR11H register)
SRPR11/ CSIPR111/ IICPR111(bit 6 of PR11H register)
(4)The following interrupt request names have been added.
INTIICA0/ INTTM11H/ INTTM13H/ INTTM10/ INTTM11/ INTTM12/ INTTM13
INTST1/ INTCSI10/ INTIIC10/ INTSR1/ INTCSI11/ INTIIC11
INTP8(64 and 48-pin products only)/ INTP9(64 and 48-pin products only)/ INTP10(64-pin products only)/ INTP11(64-pin products only)
4. Modification of Debug Information
- RL78/F13 group
- RL78/F14 group
[Contents]
The POR voltage information that a debugger uses has been modified.
Changes from V1.00.11 to V1.00.12 (Apr. 16, 2013)
1. Supported Devices Increased
- RL78/G10 group
2. SFR Information Modified
- RL78/F13 group
[Target devices]
R5F10AGF, R5F10AGG, R5F10ALF, R5F10ALG,
R5F10BAC, R5F10BAD, R5F10BAE, R5F10BAF, R5F10BAG,
R5F10BBC, R5F10BBD, R5F10BBE, R5F10BBF, R5F10BBG,
[Contents]
The following register names have been added.
- External interrupt rising edge enable register 1 (EGP1)
- External interrupt falling edge enable register 1 (EGN1)
- RL78/F14 group
[Target devices]
R5F10PAD, R5F10PAE, R5F10PBD, R5F10PBE,
[Contents]
The following register names have been added.
- External interrupt rising edge enable register 1 (EGP1)
- External interrupt falling edge enable register 1 (EGN1)
[Target devices]
R5F10PGD, R5F10PGE, R5F10PGF
[Contents]
The following attribute of register of bit3 have been changed from Read/Write to Read only.
- External interrupt rising edge enable register 1 (EGP1)
- External interrupt falling edge enable register 1 (EGN1)
Changes from V1.00.10 to V1.00.11 (Feb. 1, 2013)
1. Supported Devices Increased
- RL78/F13 group LIN products (with equal to or greater than 80 pins; or equal to or greater than 96-KB ROM)
[Target devices]
R5F10AGF, R5F10AGG, R5F10ALF, R5F10ALG,
R5F10AME, R5F10AMF, R5F10AMG
- RL78/F13 group CAN products
[Target devices]
R5F10BAC, R5F10BAD, R5F10BAE, R5F10BAF, R5F10BAG,
R5F10BBC, R5F10BBD, R5F10BBE, R5F10BBF, R5F10BBG,
R5F10BGC, R5F10BGD, R5F10BGE, R5F10BGF, R5F10BGG,
R5F10BLC, R5F10BLD, R5F10BLE, R5F10BLF, R5F10BLG,
R5F10BME, R5F10BMF, R5F10BMG,
- RL78/F14 group
[Target devices]
R5F10PPJ and
Products with equal to or less than 80 pins; or equal to or less than 96-KB ROM:
R5F10PAD, R5F10PAE, R5F10PBD, R5F10PBE,
R5F10PGD, R5F10PGE, R5F10PGF,
R5F10PLE, R5F10PLF, R5F10PME, R5F10PMF
Changes from V1.00.09 to V1.00.10 (Dec. 16, 2012)
1. Supported Devices Increased - RL78/L13 group [Target devices] R5F10WLA, R5F10WLC, R5F10WLD, R5F10WLE, R5F10WLF, R5F10WLG, R5F10WMA, R5F10WMC, R5F10WMD, R5F10WME, R5F10WMF, R5F10WMG 2. SFR Information Modified - RL78/F12 group [Target devices] R5F10968, R5F1096A, R5F1096B, R5F1096C, R5F1096D, R5F1096E [Contents] - POM0 register (address:F0050h) has been deleted. - The access attribute of PMC0 register (address: F0060H) has been changed. After change: 0bit Read Before change: 0bit Read/Write - The access attributes of TOE0L register (address: F01BAH) have been changed. After change: 5bit, 6bit and 7bit Read/Write Before change: 5bit, 6bit and 7bit Read
Changes from V1.00.08 to V1.00.09 (Nov. 1, 2012)
1. Supported Devices Increased
- RL78/D1A group
[Target devices]
R5F10CGB, R5F10CGC, R5F10CGD, R5F10CLD, R5F10CMD,
R5F10CME, R5F10DGC, R5F10DGD, R5F10DGE, R5F10DLD,
R5F10DLE, R5F10DMD, R5F10DME, R5F10DMF, R5F10DMG,
R5F10DMJ, R5F10DPE, R5F10DPF, R5F10DPG, R5F10DPJ,
R5F10TPJ
- RL78/G1C group
[Target devices]
R5F10JBC, R5F10JGC, R5F10KBC, R5F10KGC
2. SFR Information Modified
- RL78/L12 group
[Target devices]
R5F10RB8, R5F10RBA, R5F10RBC, R5F10RF8, R5F10RFA,
R5F10RFC, R5F10RG8, R5F10RGA, R5F10RGC, R5F10RJ8,
R5F10RJA, R5F10RJC, R5F10RLA, R5F10RLC
[Contents]
The access attributes of KRF register (address: FF35H) have been changed.
After change: 8bit Read/Write
Before change: 8bit Read, 1bit Read/Write
The name of the MLCD register (address: FF4CH) bit 7 has been changed.
After change: MLCDEN
Before change: LCTZS
3. Addition and Modification of Pin Configuration Information
- Addition
RL78/G12 group
RL78/G13 group
RL78/G14 group
RL78/G1A group
RL78/F12 group
RL78/I1A group
RL78/L12 group
- Modification
78K0R/Kx3
[Contents]
The I/O information indication for the pin name "CLKOUT" in the device pin list has been corrected from "I" to "O."
(78K0R/KG3, 78K0R/KH3 and 78K0R/KJ3 only)
The I/O information indication for the pin name "_RESET" in the device pin list has been corrected from "-" to "I."
Changes from V1.00.07 to V1.00.08 (July 1, 2012)
1. Supported Devices Increased
- 78K0
uPD78F8071, uPD78F8072, uPD78F8073, uPD78F8074, uPD78F8075, and uPD78F8077
2. Modification of SFR Information
- RL78/L12 group
All the MCUs in RL78/L12 group
[Contents]
The interrupt request name of the vector table address (0044H) has been changed.
Modified: INTLCD
Previous: INTLCD0
- RL78/G14 group
R5F104BD
[Contents]
The size information of ROM and RAM have been corrected as follows:
Previous |
Corrected size |
|
| ROM | 32 KB |
48 KB |
| RAM | 4 K |
5.5 KB |
Changes from V1.00.06 to V1.00.07 (May 21, 2012)
1. Supported Devices Increased - RL78/L12 group R5F10RB8, R5F10RBA, R5F10RBC, R5F10RF8, R5F10RFA, R5F10RFC, R5F10RG8, R5F10RGA, R5F10RGC, R5F10RJ8, R5F10RJA, R5F10RJC, R5F10RLA, and R5F10RLC - RL78/G14 group R5F104AF, R5F104AG, R5F104BF, R5F104BG, R5F104CF, R5F104CG, R5F104EF, R5F104EG, R5F104EH, R5F104FF, R5F104FG, R5F104FH, R5F104FJ, R5F104GA, R5F104GC, R5F104GD, R5F104GE, R5F104GF, R5F104GG, R5F104GH, R5F104GJ, R5F104JF, R5F104JG, R5F104JH, R5F104JJ, R5F104LF, R5F104LG, R5F104LH, R5F104LJ, R5F104MF, R5F104MG, R5F104MH, R5F104MJ, R5F104PF, R5F104PG, R5F104PH, and R5F104PJ 2. Modification and Addition of SFR Information - RL78/I1A group R5F1076C, R5F107AC, R5F107AE, R5F107BC, and R5F107DE On the above MCUs, BIT registers have been added as follows:
| MCU | Bit registers in item 1 below | Bit registers in item 2 below | Bit registers in item 3 below |
| R5F1076C |  |
||
| R5F107AC | |
|
|
| R5F107AE | |
|
|
| R5F107BC | |
|
|
| R5F107DE | |
|
1. The following BIT registers have been added:
INTMK00 (Address: F05C2h Bit0), INTMK01 (Address: F05C2h Bit1), INTMK02 (Address: F05C2h Bit2),
INTMK04 (AddressF05C2h Bit4)
INTMF00 (Address: F05C3h Bit0), INTMF01(F05C3h Bit1), and INTMF02(Address: F05C3h Bit2)
2. The following BIT registers have been added:
INTMK03(Address: F05C2h Bit3), INTMK05(Address: F05C2h Bit5), INTMK06(Address: F05C2h Bit6),
and INTMF03(Address: F05C3h Bit3)
3. The following BIT registers have been added:
INTMK03(Address: F05C2h Bit3), INTMK04(Address: F05C2h Bit4), INTMK05(Address: F05C2h Bit5),
and INTMF03(Address: F05C3h Bit3)
- RL78/G12 group
R5F10266, R5F10366, R5F10267, R5F10367, R5F10277, R5F10377, R5F10268
R5F10368, R5F10278, R5F10378, R5F10269, R5F10369, R5F10279, R5F10379
R6F1026A, R5F1036A, R5F1027A, and R5F1037A
The access attributes of the KRF register (Address: FF35H) have been modified as follows:
Before the change: 1st bit is with Write, and 8th bit is with Read
After the change: 8th bit is with Read and Write
Changes from V1.00.05 to V1.00.06
1. Supported Devices Increased - 78K0/Kx2-A (36-pin) uPD78F0592, uPD78F0593 - 78K0R/Fx3 uPD78F1804A, uPD78F1805A, uPD78F1806A, uPD78F1807A, uPD78F1808A, uPD78F1809A, uPD78F1810A, uPD78F1811A, uPD78F1812A, uPD78F1813A, uPD78F1814A, uPD78F1815A, uPD78F1816A, uPD78F1817A, uPD78F1818A, uPD78F1819A, uPD78F1820A, uPD78F1821A, uPD78F1822A, uPD78F1823A, uPD78F1824A, uPD78F1825A, uPD78F1826A, uPD78F1827A, uPD78F1828A, uPD78F1829A, uPD78F1830A, uPD78F1831A, uPD78F1832A, uPD78F1833A, uPD78F1834A, uPD78F1835A, uPD78F1836A, uPD78F1837A, uPD78F1838A, uPD78F1839A, uPD78F1840A, uPD78F1841A, uPD78F1842A, uPD78F1843A, uPD78F1844A, uPD78F1845A 2. SFR Information Modified - RL78/G12 group [Target devices] R5F102A7, R5F102A8, R5F102A9, R5F102AA, R5F103A7, R5F103A8, R5F103A9, R5F103AA [Contents] The register names have been changed as follows:
Table1 Change of register name |
| Register | New name |
Old name |
| IF1H register (Address:FFFE3h) bit 2 | TMKAIF | ITIF |
| MK1H register (Address:FFFE7h) bit 2 | TMKAMK | ITMK |
| PR01H register (Address:FFFEBh) bit 2 | TMKAPR0 | ITPR0 |
| PR11H register (Address:FFFEFh) bit 2 | TMKAPR1 | ITPR1 |
- RL78/G13 group [Target devices] R5F101AG [Contents] The size information of ROM and RAM has been corrected. This size information has been added in V1.00.05 and not included in V1.00.04 and earlier.
Table2 Corrected ROM/RAM size of R5F101AG |
| Size before the correction | Corrected size | |
| ROM | 96KB | 128KB |
| RAM | 8K | 12KB |
Changes from V1.00.04 to V1.00.05
1. Supported Devices Increased - 78K0R/uPD78F8058 uPD78F8056A, uPD78F8057A, uPD78F8058A - RL78/G1A group R5F10E8A, R5F10E8C, R5F10E8D, R5F10E8E, R5F10EBA, R5F10EBC, R5F10EBD, R5F10EBE, R5F10EGA, R5F10EGC, R5F10EGD, R5F10EGE, R5F10ELC, R5F10ELD, R5F10ELE 2. Modify for SFR information etc. - RL78/G13 group [Target devices] R5F1006A, R5F1016A, R5F1007A, R5F1017A, R5F1008A, R5F1018A, R5F100AA R5F101AA, R5F100BA, R5F101BA, R5F100CA, R5F101CA, R5F100EA, R5F101EA R5F100FA, R5F101FA, R5F100GA, R5F101GA [Contents] The Mirror area for the above devices has been corrected. Mirror area : Changed from F2000H- FF6FFH to F2000H--F3FFFH. [Target devices] R5F1006C, R5F1016C, R5F1007C, R5F1017C, R5F1008C, R5F1018C, R5F100AC R5F101AC, R5F100BC, R5F101BC, R5F100CC, R5F101CC, R5F100EC, R5F101EC R5F100FC, R5F101FC, R5F100GC, R5F101GC, R5F100JC, R5F101JC, R5F100LC, R5F101LC [Contents] The Mirror area for the above devices has been corrected. Mirror area : Changed from F2000H--FF6FFH to F2000H--F7FFFH. [Target devices] R5F1006D, R5F1016D, R5F1007D, R5F1017D, R5F1008D, R5F1018D R5F100AD, R5F101AD, R5F100BD, R5F101BD, R5F100CD, R5F101CD R5F100ED, R5F101ED, R5F100FD, R5F101FD, DR5F100GD, R5F101GD R5F100JD, R5F101JD, R5F100LD, R5F101LD [Contents] The Mirror area for the above devices has been corrected. Mirror area : Changed from F2000H--FF2FFH to F2000H--FBFFFH.
Changes from V1.00.03 to V1.00.04
1. Addition for the following devices. - 78K0R/Kx3-L (Addition for the following 40pin devices) uPD78F1000, uPD78F1001, uPD78F1002, uPD78F1003 - RL78/G12 group R5F10266, R5F10267, R5F10268, R5F10269, R5F1026A, R5F10277 R5F10278, R5F10279, R5F1027A, R5F102A7, R5F102A8, R5F102A9 R5F102AA, R5F10366, R5F10367, R5F10368, R5F10369, R5F1036A R5F10377, R5F10378, R5F10379, R5F1037A, R5F103A7, R5F103A8 R5F103A9, R5F103AA 2. Addition and modify for SFR information etc. - 78K0R/Lx3 group [Target devices] uPD78F1510, uPD78F1512, uPD78F1513, uPD78F1515, uPD78F1516, uPD78F1518 [Contents] Properties screen is displayed in Figure1 and click the device name in the project tree in CubeSuite+ Table1 devices have changed the file name part of the red frame in Figure 1.
Table1 Change of file name 1 |
| Devices | File name (after of change) | File name (before of change) |
| uPD78F1510 | DF1510A8.78K | DF1510A80.78K |
| uPD78F1512 | DF1512A8.78K | DF1512A80.78K |
| uPD78F1513 | DF1513AA.78K | DF1513AA0.78K |
| uPD78F1515 | DF1515AA.78K | DF1515AA0.78K |
| uPD78F1516 | DF1516AC.78K | DF1516AC8.78K |
| uPD78F1518 | DF1518AC.78K | DF1518AC8.78K |
- 78K0R/Kx3-C
[Target devices]
uPD78F1846A, uPD78F1847A, uPD78F1848A, uPD78F1849A
[Contents]
Properties screen is displayed in Figure1 and click the device name in the project tree in CubeSuite+ Table2 devices
have changed the file name part of the red frame in Figure 1.
Table2 Change of file name 2 |
| Devices | File name (after of change) | File name (before of change) |
| uPD78F1846 | DF1846A8.78K | DF1846A80.78K |
| uPD78F1847 | DF1847A8.78K | DF1847A80.78K |
| uPD78F1848 | DF1848AA.78K | DF1848AA0.78K |
| uPD78F1849 | DF1849AA.78K | DF1849AA0.78K |
| Figure 1 Properties screen of CubeSuite+ |
- RL78/G14 group
[Target devices]
Refer to Table 3
[Contents]
1. The access attribute of TT0L register (address:F01B4H) is changed.
The attribute of TT0L register from bit4 to bit7 is changed from Read/Write to Read.
2. The access attribute of TS0L register (address:F01B2H) is changed.
The attribute of TS0L register from bit4 to bit7 is changed from Read/Write to Read.
3. The access attribute of TOE0 register (address:F01BAH) is changed.
The attribute of TOE0 register from bit4 to bit7 is changed from Read/Write to Read.
4. Changed reserved area and Mirror area of R5F104AA, R5F104BA, R5F104CA, R5F104EA, R5F104FA and R5F104GA.
Reserved area : Change from 04000H to EEFFFH to EEFFFH from 10000H.
Mirror area : Change from F2000H to F3FFFH to FF4FFH from F2000H.
5. Changed reserved area and Mirror area of R5F104AC, R5F104BC, R5F104CC, R5F104EC, R5F104FC, R5F104GC,
R5F104JC and R5F104LC.
Reserved area : Change from 08000H to EEFFFH to EEFFFH from 10000H.
Mirror area : Change from F2000H to F7FFFH to FEEFFH from F2000H.
6. Changed reserved area and Mirror area of R5F104AD, R5F104BD, R5F104CD, R5F104ED, R5F104FD, R5F104GD,
R5F104JD and R5F104LD.
Reserved area : Change from 0C000H to EEFFFH to EEFFFH from 10000H.
Mirror area : Change from F2000H to FBFFFH to FE8FFH from F2000H.
Table3 Target devices and contents |
| Target devices | contents |
Pin |
|||||
1 |
2 |
3 |
4 |
5 |
6 |
||
| R5F104AA | |
|
|
|
30 |
||
| R5F104AC | |
|
|
|
30 |
||
| R5F104AD | |
|
|
|
30 |
||
| R5F104AE | |
|
|
30 |
|||
| R5F104BA | |
|
|
|
32 |
||
| R5F104BC | |
|
|
|
32 |
||
| R5F104BD | |
|
|
|
32 |
||
| R5F104BE | |
|
|
32 |
|||
| R5F104CA | |
|
|
|
36 |
||
| R5F104CC | |
|
|
|
36 |
||
| R5F104CD | |
|
|
|
36 |
||
| R5F104CE | |
|
|
36 |
|||
| R5F104EA | |
|
|
|
40 |
||
| R5F104EC | |
|
|
|
40 |
||
| R5F104ED | |
|
|
|
40 |
||
| R5F104EE | |
|
|
40 |
|||
| R5F104FA | |
|
|
|
44 |
||
| R5F104FC | |
|
|
|
44 |
||
| R5F104FD | |
|
|
|
44 |
||
| R5F104FE | |
|
|
44 |
|||
| R5F104GA | |
|
|
|
48 |
||
| R5F104GC | |
|
|
|
48 |
||
| R5F104GD | |
|
|
|
48 |
||
| R5F104GE | |
|
|
48 |
|||
| R5F104JC | |
|
|
|
52 |
||
| R5F104JD | |
|
|
|
52 |
||
| R5F104JE | |
|
|
52 |
|||
| R5F104LC | |
|
|
|
64 |
||
| R5F104LD | |
|
|
|
64 |
||
| R5F104LE | |
|
|
64 |
|||
| :Target device |
Changes from V1.00.02 to V1.00.03
1. Addition for the following devices.
- RL78/F12 group
R5F10968, R5F1096A, R5F109AA, R5F109BA, R5F109GA, R5F109LA
R5F1096B, R5F109AB, R5F109BB, R5F109GB, R5F109LB, R5F1096C
R5F109AC, R5F109BC, R5F109GC, R5F109LC, R5F1096D, R5F109AD
R5F109BD, R5F109GD, R5F109LD, R5F1096E, R5F109AE, R5F109BE
R5F109GE, R5F109LE
- RL78/I1A group
R5F107BC
2. Addition and modify for SFR information etc.
- RL78/I1A group
[Target devices]
Refer to Table 1
[Contents]
1. Changes of Flash mirror area from 000F2000H - 000FF6FFH to 000F2000H - 000FF7FFH.
2. TOEKC0 register (address: F05C8H) bit0:TOEKC00, bit1:TOETKC01, bit2:TOETKC02 and bit3:TOETKC03 are added.
3. TOEKC0 register (address: F05C8H) bit0:TOEKC00, bit1:TOETKC01, bit2:TOETKC02, bit3:TOETKC03, bit4:TOEKC04 and
bit5:TOETKC05 are added.
Table1 Target devices and contents |
Target Devices |
contents |
||
1 |
2 |
3 |
|
| R5F1076C | |
|
|
| R5F107AC | |
|
|
| R5F107AE | |
||
| R5F107DE | |
||
| :Target device |
Changes from V1.00.01 to V1.00.02
1. Addition for the following devices. - 78K0 uPD78F8014,uPD78F8015,uPD78F8016,uPD78F8017,uPD78F8018,uPD78F8019, uPD78F8020,uPD78F8026,uPD78F8027,uPD78F8028,uPD78F8029,uPD78F8030, uPD78F8032D,uPD78F8033,uPD78F8034,uPD78F8035,uPD78F8036,uPD78F8037, uPD78F8039D - 78K0R uPD78F8064,uPD78F8065,uPD78F8066,uPD78F8067,uPD78F8068,uPD78F8069 - 78K0R/Lx3-M uPD78F8070 2. Addition and modify for SFR information etc. - 78K0/Fx2 [Target devices] uPD78F0894,uPD78F0895 [Contents] Addition to BANK register (address: FFF3H). - 78K0R/Lx3 [Target devices] uPD78F1510A,uPD78F1512A,uPD78F1513A,uPD78F1515A,uPD78F1516A,uPD78F1518A [Contents] Addition to ADVRC register (address: FFF36H). - 78K0R/Kx3-C [Target devices] uPD78F1847,uPD78F1847A [Contents] The attribute of RXD2 register (address:FFF4AH) is changed from Word to Byte. - RL78/G14 [Target devices] Refer to Table 1 [Contents] 1. PMC0 register (address:F0060H) is deleted. 2. The access attribute of KRM register (address:FFF37H) is changed. The attribute of KRM register from bit4 to bit7 is changed from Read/Write to Read. 3. The setting information for subsystem clock is changed. 4. RTCC0 register (address:FFF9DH) bit5 is deleted and changed from Read/Write to Read for attribute. 5. KRM register (address: FFF37H) is deleted. 6. The access attribute of KRM register (address:FFF37H) is changed. The attribute of KRM register bit6 and bit7 is changed from Read/Write to Read. 7. The access attribute of PMC0 register (address:F0060H) is changed. The attribute of PMC0 register bit3 and bit2 is changed from Read/Write to Read. The attribute of PMC0 register bit1 and bit0 is changed from Read to Read/Write. 8. An interrupt name (INTRTC[F0036H]) is added. 9. IF1H register (address: FFFE3H) bit1 (RTCIF) is added and changed from Read to Read/Write for attribute. 10. MK1H register (address: FFFE7H) bit1 (RTCMK) is added and changed from Read to Read/Write for attribute. 11. PRO1H register (address: FFFEBH) bit1 (RTCPR0) is added and changed from Read to Read/Write for attribute. 12. PR11H register (address: FFFEFH) bit1 (RTCIPR1) is added and changed from Read to Read/Write for attribute.
Target devices R5F104AA R5F104AC R5F104AD R5F104AE R5F104BA R5F104BC R5F104BD R5F104BE R5F104CA R5F104CC R5F104CD R5F104CE R5F104EA R5F104EC R5F104ED R5F104EE R5F104FA R5F104FC R5F104FD R5F104FE R5F104GA R5F104GC R5F104GD R5F104GE
- RL78/I1A [Target devices] R5F1076C,R5F107AC,R5F107AE [Contents] The setting formation for subsystem clock is changed.