The 8530F-01 is a low skew, 1-to-16 Differential-to-3.3V LVPECL Fanout Buffer. The CLK, nCLK pair can accept most standard differential input levels. The high gain differential amplifier accepts peak-to-peak input voltages as small as 150mV as long as the common mode voltage is within the specified minimum and maximum range. Guaranteed output and part-to-part skew characteristics make the 8530F-01 ideal for those clock distribution applications demanding well defined performance and repeatability.

特性

  • Sixteen differential LVPECL output pairs
  • CLK, nCLK input pair
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Maximum output frequency: 500MHz
  • Translates any single-ended input signal to 3.3V LVPECL levels with a resistor bias on nCLK input
  • Output skew: 20ps (typical)
  • Additive phase jitter, RMS @ 106.25MHz: 0.11ps (typical)
  • Full 3.3V supply voltage
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete TQFP 48 C 是的 Tray
Availability
Obsolete TQFP 48 C 是的 Reel
Availability

文档和下载

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
8530-01 Data Sheet 数据手册 PDF 246 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB