Renesas Electronics Corporation
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557-06

Not Recommended for New Designs

2 to 4 Differential PCIe GEN1 Clock MUX

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Features

  • Packaged in 20-pin TSSOP
  • Pb (lead) free packaging
  • Operating voltage of 3.3 V
  • Low power consumption
  • Input differential clock of up to 200 MHz
  • Jitter 60 ps (cycle-to-cycle)
  • Output-to-output skew of 50 ps
  • Available in industrial temperature range (-40 to +85°C)
  • For PCIe Gen2/3 applications, see the 5V41067A
Find Other Products in Application-Specific Clocks
557-06 - Block Diagram
557-06 - Pinout
557-06 - Block Diagram
557-06 - Pinout

Description

The 557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential HCSL input pairs and fans out to four pairs of differential HCSL or LVDS outputs.

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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

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