概览

简介

CD4014BMS - synchronous parallel or serial input/serial output CD4021BMS - asynchronous parallel input or synchronous serial input/serial output CD4014BMS and CD4021BMS series types are 8-stage parallel or serial input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel JAM inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, Q outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014BMS. In the CD4021BMS serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/ SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021BMS, the CLOCK input of the internal stage is forced when an asynchronous parallel entry is made. Register expansion using multiple packages is permitted. The CD4014BMS and CD4021BMS are supplied in these 16-lead outline packages: Braze Seal DIP H4T Frit Seal DIP H1F Ceramic Flatpack H6W

特性

  • High voltage types (20V rating)
  • Medium speed operation 12MHz (Typ.) clock rate at VDD-VSS = 10V
  • Fully static operation
  • 8 master-slave flip-flops plus output buffering and control gating
  • 100% tested for quiescent current at 20V
  • Maximum input current of 1µA at 18V over full package temperature range; 100nA at 18V and +25 °C
  • Noise margin (full package temperature range)
  • 1V at VDD = 5V
  • 2V at VDD = 10V
  • 2.5V at VDD = 15V
  • Standardized symmetrical output characteristics
  • 5V, 10V and 15V parametric ratings
  • Meets all requirements of JEDEC tentative standard No. 13B, "Standard Specifications for Description of "B" Series CMOS devices

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文档

类型 文档标题 日期
数据手册 PDF 367 KB
手册 PDF 467 KB
手册 PDF 4.85 MB
Price Increase Notice PDF 360 KB
其他
白皮书 PDF 533 KB
Product Advisory PDF 499 KB
产品变更通告 PDF 230 KB
应用文档 PDF 338 KB
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设计和开发

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