The 71124 5V CMOS SRAM is organized as 128K x 8. The JEDEC centerpower/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71124 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.

特性

  • JEDEC revolutionary pinout (center power/GND) for reduced noise.
  • Equal access and cycle times – Commercial and Industrial: 12/15/20ns
  • One Chip Select plus one Output Enable pin
  • Bidirectional inputs and outputs directly TTL-compatible
  • Low power consumption via chip deselect
  • Available in a 32-pin 400 mil Plastic SOJ packages

tune产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active SOJ 32 C 是的 Tube
Availability
Active SOJ 32 C 是的 Reel
Availability
Active SOJ 32 C 是的 Tube
Availability
Active SOJ 32 C 是的 Reel
Availability
Active SOJ 32 I 是的 Tube
Availability
Active SOJ 32 I 是的 Reel
Availability
Active SOJ 32 C 是的 Tube
Availability
Active SOJ 32 C 是的 Reel
Availability
Active SOJ 32 I 是的 Tube
Availability
Active SOJ 32 I 是的 Reel
Availability

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star 71124 Data Sheet 数据手册 PDF 87 KB

file_download下载

文档标题 language 类型 文档格式 文件大小 日期
模型
71124 IBIS Model 模型 - IBIS ZIP 5 KB