The 2510C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The 2510C operates at 3.3V VCC and drives up to ten clock loads.
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类型 | 文档标题 | 日期 |
数据手册 | PDF 214 KB | |
产品变更通告 | PDF 611 KB | |
产品变更通告 | PDF 611 KB | |
产品变更通告 | PDF 95 KB | |
产品变更通告 | PDF 50 KB | |
产品变更通告 | PDF 361 KB | |
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