The 5L35023 is a VersaClock programmable clock generator and is designed for low power, consumer, and high performance PCI Express applications. The 5L35023 device is a three PLL architecture design, and each PLL is individually programmable and allowing for up to five unique frequency outputs.

The 5L35023 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshot Reduction Technology (ORT) and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after power up, then program the 5L35023 again through the I²C interface.

The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization base on the application requirements. It also supports three single-ended output and two pair of differential outputs that support LVCMOS and LPHCSL. A Low Power 32.768kHz clock is supported with only less than 2μA current consumption for system RTC reference clock.
 

特性

  • Configurable OE pin function as OE, PD#, PPS or DFC control function
  • Configurable PLL bandwidth/minimizes jitter peaking
  • PPS: Proactive Power Saving features save power during the end device power down mode
  • PPB: Performance- Power Balancing feature allows minimum power consumption base on required performance
  • DFC: Dynamic Frequency Control feature allows up to 4 difference frequencies switch dynamically
  • Features < 65µA ultra-power-down
  • Outputs: 1MHz to 125MHz
  • Spread Spectrum clock support to lower system EMI
  • I²C interface

产品选择

This device is factory-configurable. Try the Custom Part Configuration Utility.
器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 24 I 是的 Tray
Availability
Active VFQFPN 24 I 是的 Reel
Availability

Product Comparison

5L35023 5L35021 5P35021 5P35023
Inputs (#) 1 1 1 1
Output Type LP-HCSL, LVCMOS LP-HCSL, LVCMOS LP-HCSL, LVCMOS, LVDS, LVPECL LP-HCSL, LVCMOS, LVDS, LVPECL
Core Voltage (V) 1.8 1.8 3.3 3.3
Output Voltage (V) 1.8 1.8 1.8, 2.5, 3.3 1.8, 2.5, 3.3
Pkg. Dimensions (mm) 4.0 x 4.0 x 0.9 3.0 x 3.0 x 1.0 3.0 x 3.0 x 1.0 4.0 x 4.0 x 0.9

文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
5L35023 Datasheet 数据手册 PDF 630 KB
使用指南与说明
Timing Commander Installation Guide 指南 PDF 497 KB
应用指南 & 白皮书
AN-909 PCB Layout Considerations for Designing IDT VersaClock 3S, 5 and 6 Clock Products 应用文档 PDF 901 KB
AN-918 Programmable Clocks vs Crystal Oscillators 应用文档 PDF 307 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs 应用文档 PDF 480 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-808 PCI Express/HCSL Termination 应用文档 PDF 137 KB
PCN / PDN
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel
产品变更通告 PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel
产品变更通告 PDF 5.61 MB
PCN# : TP1910-01 VBAT Power Domain Required 产品变更通告 PDF 110 KB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
其他
VersaClock Family Overview 日本語 概览 PDF 376 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
VersaClock 3S Timing Commander Personality File 软件 ZIP 5.80 MB
Timing Commander Installer (v1.16.4) 软件 ZIP 19.79 MB
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs 技术摘要 PDF 238 KB

下载

文档标题 language 类型 文档格式 文件大小 日期
模型
5L35023 IBIS Model 模型 - IBIS ZIP 27 KB

开发板与套件

器件号 文档标题 类型 Company
DEV5L35023 5L35023 VersaClock 3S Programmable Clock Development Kit 开发 Renesas