The 87608I has a selectable REF_CLK or crystal input. The REF_CLK input accepts LVCMOS or LVTTL input levels. The 87608I has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiplying and regenerating clocks with "zero delay". The 87608I is a 1:8 PCI/PCI-X Clock Generator. The 87608I has a selectable REF_CLK or crystal input. The REF_CLK input accepts LVCMOS or LVTTL input levels. The 87608I has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiplying and regenerating clocks with "zero delay". The PLL's VCO has an operating range of 250MHz-500MHz, allowing this device to be used in a variety of general purpose clocking applications. For PCI/PCI-X applications in particular, the VCO frequency should be set to 400MHz. This can be accomplished by supplying 33.33MHz, 25MHz, 20MHz, or 16.66MHz on the reference clock or crystal input and by selecting ÷12, ÷16, ÷20, or ÷24, respectively as the feedback divide value. The dividers on each of the two output banks can then be independently configured to generate 33.33MHz (÷12), 66.66MHz (÷6), 100MHz (÷4), or 133.33MHz (÷3). The 87608I is characterized to operate with its core supply at 3.3V and each bank supply at 3.3V or 2.5V. The 87608I is packaged in a small 7x7mm body LQFP, making it ideal for use in space-constrained applications.

特性

  • Fully integrated PLL
  • Eight LVCMOS/LVTTL outputs, 15? typical output impedance
  • Selectable crystal oscillator interface or LVCMOS/LVTTL REF_IN clock input
  • Maximum output frequency: 166.67MHz
  • Maximum crystal input frequency: 38MHz
  • Maximum REF_IN input frequency: 41.67MHz
  • Individual banks with selectable output dividers for generating 33.333MHz, 66.66MHz, 100MHz and 133.333MHz
  • Separate feedback control for generating PCI / PCI-X frequencies from a 16.66MHz or 20MHz crystal, or 25MHz or 33.33MHz reference frequency
  • VCO range: 200MHz to 500MHz
  • Cycle-to-cycle jitter: 120ps (maximum), @ 3.3V
  • Period jitter, RMS: 20ps (maximum)
  • Output skew: 250ps (maximum)
  • Bank skew: 60ps (maximum)
  • Static phase offset: 160ps ± 160ps
  • Voltage Supply Modes:
    VDD (core/inputs), VDDA (analog supply for PLL),
    VDDOA (output bank A),
    VDDOB (output bank B, REF_OUT, FB_OUT)
    VDD/VDDA/VDDOA/VDDOB
    3.3/3.3/3.3/3.3
    3.3/3.3/2.5/3.3
    3.3/3.3/3.3/2.5
    3.3/3.3/2.5/2.5
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free RoHS compliant package

产品选择

下单器件型号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete TQFP 32 I 是的 Tray
Availability
Obsolete TQFP 32 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
87608I Datasheet 数据手册 PDF 245 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : CQ-19-01(R1) Quarterly Market Declined PDN 产品停产通告 PDF 1014 KB
PDN# : CQ-19-01 Quarterly Market Declined PDN 产品停产通告 PDF 537 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 50 KB
PCN# : A1401-02 Alternate Copper Wire Assembly Site 产品变更通告 PDF 36 KB
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 363 KB
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 产品变更通告 PDF 472 KB
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 209 KB
下载
87608I IBIS Model 模型 - IBIS ZIP 67 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB