The 831721I is a high-performance, differential HCSL clock/data multiplexer and fanout buffer. The device is designed for the multiplexing of high-frequency clock and data signals. The device has two differential, selectable clock/data inputs. The selected input signal is output at one differential HCSL output. Each input pair accepts HCSL, LVDS, and LVPECL levels. The 831721I is characterized to operate from a 3.3V power supply. Guaranteed input, output-to-output and part-to-part skew characteristics make the 831721I ideal for those clock and data distribution applications demanding well-defined performance and repeatability. The 831721I supports the clock multiplexing and distribution of PCI Express Generation 1, 2 and 3 clock signals.

特性

  • 2:1 differential clock/data multiplexer with fanout
  • Two selectable, differential inputs
  • Each differential input pair can accept the following levels: HCSL, LVHSTL, LVDS and LVPECL
  • One differential HCSL output
  • Maximum input/output clock frequency: 700MHz (maximum)
  • Maximum input/output data rate: 1400Mb/s (NRZ)LVCMOS interface levels for all control inputs
  • Input skew: 55ps (maximum)
  • Part-to-part skew: 400ps (maximum)
  • Full 3.3V supply voltage
  • Available in lead-free (RoHS 6) 16 TSSOP package
  • -40°C to 85°C ambient operating temperature

tune产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete TSSOP 16 I 是的 Tube
Availability
Obsolete TSSOP 16 I 是的 Reel
Availability

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star ICS831721I FINAL DATASHEET 数据手册 PDF 914 KB
应用指南 & 白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : CQ-19-01(R1) Quarterly Market Declined PDN 产品停产通告 PDF 1014 KB
PDN# : CQ-19-01 Quarterly Market Declined PDN 产品停产通告 PDF 537 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 544 KB
PCN# : TB1403-01 Changed in Carrier Tape, Plastic Reel and Quantity per Reel on TSSOP-14, TSSOP-16 产品变更通告 PDF 663 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 产品变更通告 PDF 361 KB
其他
Clock Distribution Overview 概览 PDF 217 KB
IDT Clock Generation Overview 概览 PDF 1.83 MB

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