The 8P34S2102 is a high-performance, low-power, differential dual 1:2 LVDS Output 1.8V / 2.5V Fanout Buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. Two independent buffer channels are available, each channel has two low skew outputs. High isolation between channels minimizes noise coupling. AC characteristics such as propagation delay are matched between channels. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S2102 ideal for those clock distribution applications demanding well-defined performance and repeatability. The device is characterized to operate from a 1.8V / 2.5V power supply. The integrated bias voltage references enable easy interfacing of AC-coupled signals to the device inputs.

特性

  • Dual 1:2 low skew, low additive jitter LVDS fanout buffers
  • Matched AC characteristics across both channels
  • High isolation between channels
  • Low power consumption
  • Both differential CLKA, nCLKA and CLKB, nCLKB inputs accept LVDS, LVPECL and single-ended LVCMOS levels
  • Maximum input clock frequency: 2.0GHz
  • Output amplitudes: 350mV, 500mV (selectable)
  • Output bank skew: 5ps typical
  • Output skew: 30ps typical
  • Low additive phase jitter, RMS: 40fs typical (fREF = 156.25MHz, 12kHz to 20MHz)
  • Full 1.8V / 2.5V supply voltage mode
  • Lead-free (RoHS 6), 16-lead VFQFN packaging
  • -40°C to 85°C (Tc ≤ 105°C) operating temperature range

description文档

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
star 8P34S2102 Datasheet 数据手册 PDF 558 KB
应用指南 & 白皮书
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : TB1912-02(R1) Convert Shipping Media from Tube or Tray to Cut Reel 产品变更通告 PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media from Tube or Tray to Cut Reel 产品变更通告 PDF 5.61 MB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
PCN# : A1809-04 Add Alternate Assembly Location for QFN packages 产品变更通告 PDF 36 KB
其他
RF Timing Family Product Overview 概览 PDF 331 KB
Clock Distribution Overview 概览 PDF 217 KB
8P34S21xx-series 1.8V Dual RF Clock / Data Fanout Buffers 产品简述 PDF 291 KB
IDT Clock Generation Overview 概览 PDF 1.83 MB

file_download下载

文档标题 language 类型 文档格式 文件大小 日期
模型
8P34S2102 IBIS Model 模型 - IBIS ZIP 31 KB