The 8V19N491-36 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer. The device is designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, and LTE-A radio board implementations. The device supports JESD204B subclass 0 and 1 clocks. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency.

The 8V19N491-36 supports the clock generation of high-frequency clocks from the selected VCO and low-frequency synchronization signals (SYSREF). SYSREF signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The four redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers, and phase adjustment capabilities are added for flexibility. The device is configured through a 3/4-wire SPI interface and reports lock and signal loss status in internal registers and via a lock detect (LOCK) output. Internal status bit changes can also be reported via the nINT output. The 8V19N491-36 is ideal for driving converter circuits in wireless infrastructure, radar/imaging, and instrumentation/medical applications.

For information regarding evaluation boards and material, please contact your local sales representative.


  • High-performance clock RF-PLL with support for JESD204B
  • Optimized for low phase noise: -152.5dBc/Hz (800kHz offset; 245.76MHz clock)
  • Integrated phase noise of 65fs RMS typical (12kHz–20MHz) at 737.28MHz
  • Dual-PLL architecture
  • First PLL stage with external VCXO for clock jitter attenuation
  • Second PLL with internal FemtoClock NG PLL: 3686.4MHz
  • Five output channels with a total of 18 outputs
  • Configurable integer clock frequency dividers
  • Supported clock output frequencies include: 3686.4, 1843.2, 1228.8, 737.28, 614.4, 368.4, 307.2, 245.76, 153.6, 122.88 and 61.44 MHz
  • Low-power LVPECL/LVDS outputs support configurable signal amplitude
  • Phase delay circuits
  • Redundant input clock architecture with four inputs including input activity monitoring and switching
  • SYSREF generation modes include internal and external trigger mode for JESD204B
  • Supply voltage: 3.3V
  • SPI Interface, 3/4 wire configurable
  • Package: 11 × 11 mm, 100-CABGA
  • Temperature range: -40°C to +85°C


器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active CABGA 100 I 是的 Tray
Active CABGA 100 I 是的 Reel


文档标题 language 类型 文档格式 文件大小 日期
8V19N491-36 Datasheet 数据手册 PDF 1.86 MB
8V19N49x Hardware Design Guide 指南 PDF 947 KB
应用指南 & 白皮书
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
RF Timing Family Product Overview 概览 PDF 331 KB
8V19N49x RF Sampling Clocks with Jitter Attenuation Overview 概览 PDF 1.21 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB


文档标题 language 类型 文档格式 文件大小 日期
8V19N480-490 Timing Commander Personality File (v5.1.0) 软件 ZIP 4.59 MB
8V19N491-36 IBIS Model 模型 - IBIS ZIP 270 KB