The 8SLVS1118 is a high-performance, low-power, differential 1:18 output fanout buffer. This highly versatile device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVS1118 ideal for clock distribution applications that demand well-defined performance and repeatability. The device is characterized to operate from a 2.5V or 3.3V power supply. The integrated bias voltage references enable easy interfacing AC-coupled signals to the device inputs.

特性

  • 1:18, low skew, low additive jitter LVPECL/LVDS fanout buffer 
  • Low power consumption 
  • Differential PCLK, nPCLK clock pair accepts the following differential/single-ended input levels: LVDS, LVPECL, and LVCMOS 
  • Maximum input clock frequency: 2GHz 
  • Propagation delay: 290ps (typical) 
  • Output skew: 40ps (typical) 
  • Low additive phase jitter, RMS: 39fs (typical)
  • Integration range: 12kHz–20MHz (fREF = 156.25MHz, VPP = 1V, VDD = 3.3V) 
  • Full 2.5V and 3.3V supply voltage modes 
  • Device current consumption:
    • 180mA (typical) IEE for LVPECL output mode
    • 400mA (typical) IDD for LVDS output mode 
  • 48-VFQFN, lead-free (RoHS 6) packaging 
  • Transistor count: 1762
  • -40°C to +85°C ambient operating temperature 
  • Supports case temperature up to 105°C

产品选择

下单器件 ID Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active 48 I 是的 Tray
Availability
Active 48 I 是的 Reel
Availability
Active 48 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
8SLVS1118 Datasheet 数据手册 PDF 666 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
Downloads
8SLVS1118 IBIS Model 模型 - IBIS ZIP 55 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
RF Timing Family Product Overview 概览 PDF 464 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB