The 9ZML1253E is a second generation enhanced performance DB1200ZL derivative. The part is a pin-compatible
upgrade to the 9ZML1232B, while offering a much improved phase jitter performance. A fixed external feedback maintains low drift for critical QPI/UPI applications, while each input channel has software adjustable input-to-output delay to ease transport delay management for today's more complex server topologies. The 9ZML1253E has an SMBus Write Lockout pin for increased device and system security.
特性
- SMBus write lock feature; increases system security
- 2 software-configurable input-to-output delay lines; manage transport delay for complex topologies
- LP-HCSL outputs with 85Ω Zout; eliminate 48 resistors, save 82mm² of area
- 12 OE# pins; hardware control of each output
- 3 selectable SMBus addresses; multiple devices can share same SMBus segment
- Selectable PLL bandwidths; minimizes jitter peaking in cascaded PLL topologies
- Hardware/SMBus control of PLL bandwidth and bypass; change mode without power cycle
- Spread spectrum compatible; tracks spreading input clock for EMI reduction
- 100MHz PLL Mode; UPI support
- 10 x 10 mm 72-VFQFPN package; small board footprint