The 9QXL2001 is a 20-output very-low-additive phase jitter fanout buffer for PCIe Gen4, Gen5 and UPI applications. The 9QXL2001 provides two methods to control output enables; standard OE# pins and SMBus enable bits, or a simple 3-wire serial interface that is independent of the SMBus. The OE Control Mode is set via a hardware strap. It offers integrated terminations for 85Ω transmission lines.
 

特性

  • Traditional 8 OE# pins allow hardware control of 8 outputs and 20 SMBus bits allow software control of each output
  • Simple 3-wire Side-Band Interface allows real-time control of all 20 outputs
  • Outputs remain Low/Low when powered up with floating input clock
  • Low-Power HCSL (LP-HCSL) outputs reduce device power consumption by 50%
  • Zo = 85Ω outputs eliminate 80 resistors, saving 130mm2 of area
  • 9 selectable SMBus addresses
  • Spread spectrum compatible
  • 6 × 6 mm dual-row 80-GQFN

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9QXL2001BNHGI
Active VFQFPN 80 I 是的 Tray
Availability
9QXL2001BNHGI8
Active VFQFPN 80 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
9QXL2001B Datasheet 数据手册 PDF 449 KB
应用指南 &白皮书
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5 应用文档 PDF 244 KB
AN-975 Cascading PLLs 应用文档 PDF 255 KB
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs 应用文档 PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL 应用文档 PDF 235 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-808 PCI Express/HCSL Termination 应用文档 PDF 137 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
下载
9QXL2001B IBIS Model 模型 - IBIS ZIP 36 KB
其他
9QXL2001B Schematic 原理图 PDF 78 KB
PCI Express Timing Solutions Overview 概览 PDF 275 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB