The 9QXL2000B is a 20-output very-low-additive phase jitter fanout buffer for PCIe Gen4 and Gen5. It offers integrated terminations for 85Ω transmission lines with individual output impedance trim and via SMBus registers.
 

特性

  • Low-Power HCSL (LP-HCSL) 85Ω outputs eliminate 80 resistors, saving 130mm2 of area
  • Low-Power HCSL (LP-HCSL) outputs reduce device power consumption by 50%
  • 8 OE# pins configurable to control up to 20 outputs
  • 9 selectable SMBus addresses
  • Spread spectrum compatible
  • 10 × 10 mm 72-VFQFPN package

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9QXL2000BNLGI
Active VFQFPN 72 I 是的 Tray
Availability
9QXL2000BNLGI8
Active VFQFPN 72 I 是的 Reel
Availability

文档和下载

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
9QXL2000B Datasheet 数据手册 PDF 354 KB
应用指南 &白皮书
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5 应用文档 PDF 244 KB
AN-975 Cascading PLLs 应用文档 PDF 255 KB
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs 应用文档 PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL 应用文档 PDF 235 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-808 PCI Express/HCSL Termination 应用文档 PDF 137 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
下载
9QXL2000B IBIS Model 模型 - IBIS ZIP 37 KB
其他
9QXL2000B Schematic 原理图 PDF 101 KB
PCI Express Timing Solutions Overview 概览 PDF 275 KB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB