The ADC1413D080HN is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power at sample rates of 80 Msps. Pipelined architecture and output error correction ensure the ADC1413D080HN is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a 3.3 V source for analog and a 1.8 V source for the output driver, it has two serial outputs, because of the two lanes of differential outputs, which are compliant with the JESD204A standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC. A set of IC configurations is also available via the binary level control pins taken, which are used at power-up.

特性

  • 2 configurable serial outputs
  • 3.3 V, 1.8 V single supplies
  • Compliant with JESD204A serial transmission standard
  • Dual channel 14-bit pipelined ADC core
  • Duty cycle stabilizer
  • Flexible input voltage range: 1 V (p-p) to 2 V (p-p) with 6 dB programmable fine
  • gain
  • High IF capability
  • Input bandwidth, 600 MHz
  • Offset binary, 2's complement, gray code
  • Power dissipation, 995 mW at 80 Msps
  • Power-down and Sleep modes
  • Sample rate up to 80 Msps
  • SFDR, 90 dBc
  • SNR, 73 dB
  • SPI interface

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
ADC1413D080HN-C1
Obsolete VFQFPN 56 I 是的 Tray
Availability
ADC1413D080HN-C18
Obsolete VFQFPN 56 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
ADC1413D SER Datasheet 数据手册 PDF 660 KB
PCN / PDN
PDN# : DC-14-07 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 528 KB

开发板与套件

器件号 文档标题 类型 Company
ADC1413D080W1 ADC1413D080W1 Demo board With FPGA 演示 Renesas
ADC1413D080W2 ADC1413D080W2 demo board, Lattice ECP3 on board 演示 Renesas
ADC1413D080WO ADC1413D080W0 demoboard; compliant with Lattice, Altera, Xilinx FPGA boards through specific connectors 演示 Renesas