The ADC1412D125HN is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1412D is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. It supports the LVDS (Low Voltage Differential Signaling) DDR (Double Data Rate) output standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC. The device also includes a programmable gain amplifier with a flexible input voltage range.

特性

  • CMOS or LVDS DDR digital outputs
  • Dual-channel14-bit pipelined ADC core
  • Duty cycle stabilizer
  • Fast OTR detection
  • Flexible input voltage range: 1 V to 2 V (p-p) with 6 dB programmable fine
  • gain
  • INL &plusmn
  • 1 LSB, DNL &plusmn
  • 0.5 LSB (typical)
  • Input bandwidth, 650 MHz
  • Offset binary, 2's complement, gray code
  • Power dissipation, 775 mW at 80 Msps
  • Power-down and Sleep modes
  • Sample rate up to 125 Msps
  • SFDR, 90 dBc
  • Single 3 V supply
  • SNR, 73 dB
  • SPI Interface

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete VFQFPN 64 I 是的 Tray
Availability
Obsolete VFQFPN 64 I 是的 Reel
Availability

文档和下载

文档标题 language 类型 文档格式 文件大小 日期
数据手册与勘误表
ADC1412D SER Datasheet 数据手册 PDF 600 KB
PCN / PDN
PDN# : DC-14-07 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 528 KB

开发板与套件

器件号 文档标题 类型 Company
ADC1412D125F1 ADC1412D125F1 demo board; CMOS version; SPI, Regulators and CMOS buffer on board 演示 Renesas
ADC1412D125F2 ADC1412D125F2 demo board; LVDS version; SPI, Regulators and LVDS outputs on board 演示 Renesas