DDR Zero Delay Clock Buffer

特性

  • Low skew, low jitter PLL clock driver
  • Max frequency supported = 266MHz (DDR 533)
  • I2C for functional and output control
  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • 3.3V tolerant CLK_INT input

产品选择

器件号 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
93732AFLF
Package Info
 Obsolete SSOP 28 C 是的 Tube
Availability
Buy / Quote
93732AFLFT
Package Info
 Obsolete SSOP 28 C 是的 Reel
Availability
Buy / Quote

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
93732 Datasheet – 数据手册 PDF 205 KB
应用指南 &白皮书
AN-828 Termination - LVPECL – 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers – 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection – 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals – 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations – 应用文档 PDF 153 KB
AN-827 Application Relevance of Clock Jitter – 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units – 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads – 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1305-01 Gold Wire to Copper Wire – 产品变更通告 PDF 148 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products – 产品变更通告 PDF 361 KB
PDN# : K-08-09 PRODUCT DISCONTINUANCE NOTICE – 产品删除通告 PDF 47 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
info: For device-specific or order-specific documentation, submit a support request.