概要

説明

The 72V3632 is a 3.3V version of the 723632. Two independent 512 x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

特長

  • Supports clock frequencies up to 100 MHz
  • Fast access times of 6.5ns
  • Two independent clocked FIFOs buffering data in opposite directions
  • Programmable Almost-Full and Almost-Empty flags
  • Microprocessor Interface Control Logic
  • Select IDT Standard timing or First Word Fall Through timing
  • Available in 120-pin TQFP package
  • Industrial temperature range (–40C to +85C) is available

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