The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
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Pkg. Type |
Lead Count (#) |
Temp. Grade |
Pb (Lead) Free |
Carrier Type |
ご購入 / サンプル |
|
---|---|---|---|---|---|---|
型名 | ||||||
TSSOP | 56 | C | No | Tube | ||
TSSOP | 56 | C | No | Reel | ||
TSSOP | 56 | C | Yes | Tube | ||
TSSOP | 56 | C | Yes | Reel | ||
TSSOP | 56 | C | No | Tube | ||
TSSOP | 56 | C | No | Reel | ||
TSSOP | 56 | I | No | Tube | ||
TSSOP | 56 | I | No | Reel | ||
TSSOP | 56 | I | Yes | Tube | ||
TSSOP | 56 | I | Yes | Reel | ||
TSSOP | 56 | C | No | Tube | ||
TSSOP | 56 | C | No | Reel |