インタフェース&コネクティビティ

Renesasが提供するPCIe® Gen3用リタイマの製品ファミリは、最高レベルのアナログ性能と少ない消費電力を実現しています。また、要求の厳しいコンピュータ、ストレージ、通信といった分野で、2.5Gbps、5Gbps、8Gbpsの伝送速度を必要とするアプリケーション向けに最適化されたシステムレベルの信号リタイマ機能の大半を提供しています。

RenesasのPCIe用リタイマは以下のような機能を備えています。

  • 8/16/32チャンネルの信号リタイマ(PCIeの4/8/16レーン)
  • 高度なシグナルコンディショニング機能
  • 高度な診断機能
  • プロトコルに特化した機能
  • 高度な省電力機能
  • プログラミング用のI2Cインタフェース
  • 民生用/産業用の温度範囲に対応

Download: IDT Signal Integrity Products Overview (PDF)

業界を牽引するPCIe用リタイマ

RenesasのPCIe用リタイマ(シグナルコンディショナ)は、ケーブルやプリント基板のトレースが長いシステムの性能と信頼性を向上し、シグナルインテグリティを確保するために使用します。また、入力信号からランダムジッターと確定的ジッターを取り除いてシンボル間干渉を排除し、出力ジッターバジェットをリセットします。RenesasのPCIe用リタイマには、8GT/s(Transfer/sec)のPCI Express 3.0に対応する差動チャンネルを8/16/32系統備えるデバイスが用意されており、それぞれ4/8/16レーンに対応しています。また、5GT/s、2.5GT/sのPCI Expressの機能をすべてサポートしています。

RenesasのPCIe用リタイマは、CDR(クロックデータリカバリ)アーキテクチャ、適応型のDFE(Decision Feedback Equalizer)、シリアルインタフェースによってアクセスされる多様な制御オプションで構成されています。各チャンネルに小型コントローラを備えており、イコライゼーションのトレーニングを行ったうえで、自動調節によって最高の性能が得られるよう自己構成が行えます。小型コントローラは、各リンクについて、128b/130bによる符号化、PCIe Gen1/2との互換性を保つためのダウンシフト、レシーバの検出、終端制御などの機能の制御を行います。

RenesasのPCIe用リタイマは、いずれも非線形/適応型の多段イコライザ、アナログフロントエンド、5タップのDFEを搭載しています。DFEの帰還フィルタは、前のシンボルからのISI(Inter-symbol Interference)歪みを完全に取り除き、デジタルイコライゼーションによってフィルタの出力のノイズを除去します。フィルタのタップに対する重みづけは、構成用のシリアルインタフェースによって調整できます。

イコライザ、ディエンファシス、送信信号のフルスケール振幅のデフォルト値は、ピンプログラマブルに設定可能です。PCIe用リタイマはSMBusやI2Cのスレーブデバイスとして機能させることができます。その場合、各インタフェースによってあらゆる機能/動作の構成が行えます。マスターモードで動作させれば、構成用のデータをEEPROMからダウンロードできます。また、シリアルバスによって多くのステータスレジスタを確認することも可能です。

PCIe用リタイマの信号終端はデフォルトでは100Ω(公称値)に設定されています。これは、必要に応じて85Ω(公称値)にプログラムすることも可能です。入力信号の検出に使うしきい値は、有効な信号のレベルに応じて調節できるとともに、アイドリング信号をサポートします。

また、RenesasのPCIe用リタイマは、基板のテストを容易に行えるようにするために、JTAG/AC JTAGをサポートしています。加えて、実験やフィールドテストを容易化できるようパターンジェネレータも内蔵しています。さらにはテスト/デバッグ用に、デバイスの構成情報を設定/保存するためのPC向けユーティリティや、遠隔でのフィールド診断を支援するアイダイアグラムのキャプチャツールなど、さまざまなソフトウェアも用意されています。

リタイマICは、電源電圧として1.0V、1.8V、3.3Vを使用します。また、各リンクのASPM(Active State Power Management)など、省電力化に向けたさまざまな機能も備えています。

PCIe用リタイマについて
高速信号の品質は、トランスミッタ、レシーバ、チャンネルの特性が原因で、最終的にレシーバに到達するまでに、許容できないレベルにまで低下する場合があります。PCIe用リタイマは、ケーブルやプリント基板のトレースにおける減衰とISI(Inter-symbol Interference)ジッターを補償し、ターゲットとなるレシーバにおけるジッターを最小化してアイの開きを最大化します。これは、送信信号を増幅するか、受信信号をイコライズするかによって行われます。チャンネル長が長かったり、ビアやコネクタによって不連続性が生じていたりするためにいずれか一方だけでは十分な効果が得られない場合には両方が適用されます。Renesas社のリタイマICは、ブレードサーバー、エンタープライズ向けストレージ、通信システム、クラウドコンピューティングなどのアプリケーションにおけるシグナルインテグリティの課題を解決するうえで最適な製品となっています。

ビデオ&トレーニング

IDT PCIe 3.0 Retimers for High-Speed 8Gbps Signal Conditioning

Description

IDT PCI Express 3.0 retimer for high-speed signal conditioning up to 8Gbps. Delivers signal quality over extended distances while offering simplified design by alleviating board layout constraints. These devices incorporate advanced receive equalization and transmit de-emphasis capabilities, as well as diagnostic features that help IDT customers achieve a simplified design with faster time-to-market. The devices all offer power savings modes for the lowest-possible power consumption. Presented by Ken Curt, Product Manager, Integrated Device Technology, Inc. Learn more at www.idt.com/go/PCIeSIP.

Transcript

Hi, My name's Ken Curt . I'm project manager for IDT's Signal Integrity product line. Today I'd like to talk about our PCI Express 3.0 Retimer products for high speed eight gigabit per second signal conditioning.
 
What I'm showing here is a diagram of a server. Now this diagram shows multiple uses for IDT Signal Conditioning products, including for SAS, SATA, USB 3.0 and other protocols. However, in the middle of this picture, with the bright red border, shows our PCI Express Gen3 Retimer. And in this case, you see it's connected up to IDT's new Enterprise Flash Controller as one example application.
 
Another common application is the use of signal conditioners in blade servers. This diagram shows the signal conditioner on each of two blades within the chassis, and the purpose of the conditioner is to get the signal across this long back plane, which can be up to 20 inches or even 30 inches of trace, when the trace on the blades themselves is considered. So crossing a trace of that long with two connectors in the path is a challenge, especially at eight gigabit per second PCI Express. And that's the purpose for IDT's Retimer Product. In this case, it's shown as the TO816P, which is an eight lane 16-channel Retimer. 
 
This slide shows the block diagram of our Retimer, again, the 16-channel device. You can see, going from top to bottom, the 16 lanes. But at the very top, the interface to the real world, the physical layer interface, begins with the receiver and transmitter equalizers. Below that you'll see the serializer, deserializer, the SerDes. And below that you'll see a micro-controller. Each channel of this device has its own micro-controller for coordinating various initialization and power management functions in real-time, within this device. As we go below the micro-controller, you'll see a routing function. That supports simple routing, such as lane reversal, polarity swapping, and other simple things that are like that. It's not a packet switch, of course. Off to the right side of this image, you'll see the two I2C or SMBus ports. There's a master and slave port, to give complete flexibility in your system application. And below that you'll see the configuration vector, which is important to achieving the very low 10^-12 error rate that PCI Express Gen3 automatically negotiates to. There’s also a JTAG interface, and immediately below that you see the clock. A retimer device, of course, requires a reference clock input.
 
To hit the highlights of our Gen3 Retimer, first of all, it's fully PCI Express Gen3 specification compliant. It's also fully downwards compatible to the 5-gigabit and Gen2 and 2.5-gigabit Gen1 specifications. I showed earlier one version of this device, the 16 channel version. We're actually planning for two versions of the product. There's the 16 channel version, which will come in a 196-pin BGA package. There's also the 100-pin BGA package which is footprint compatible with our four-lane repeater device. So that's a four-lane retimer which is the T0808P version. To go into the rest of the features, the receiver begins with a high-sensitivity, of course, high-speed analog CTLE Equalizer Stage, or continuous linear equalizer, and that's followed by a decision feedback equalizer, a DFE, or a digital equalizer stage. That exceeds PCI Express Gen3 specifications and provides the compensation for channel loss and jitter, and ISI or intersymbol interference that's picked up from vias and other discontinuities, connectors and things like that in the channel.  The transmitter portion of this device includes a four-tap FIR filter. This also exceeds PCI Express Gen3 requirements and its purpose is to support output waveform shaping or pre-compensation of the signal for driving across long traces. Not only can we adjust the transmit amplitude, we can adjust the waveform characteristics, or shape, we can adjust the slew rates, as well as the IO terminations for input and output. So there's tremendous flexibility in the IO capabilities and configuration of this device. A very important function, and unique to PCI Express Gen3, is the automatic negotiation process for Gen3 configuration parameters. So the receiver, equalizer and the transmitter stage all have to be configured. This is handled by a new procedure or protocol within the PCI Express Gen3 standard. In addition to the automatic equalization, our device automatically adapts for different rate changes and optimizes for the actual rate of operation. So for example, if someone plugs in a Gen1 host plus adapter or graphics card, for example, our device will optimize for the 2.5 gigabit per second data rate. Very important at the high eight-gigabit per second performance is automatic calibration. So our retimers automatically calibrate for output skews, they'll calibrate the termination impedances and other functions within this device to make the signals and the timing as close to ideal as possible. Of course, at eight gigabits per second, all these margins become very important. Our device has full support for automatic power-saving states, such as the L0S state that Intel's been promoting heavily, lately. If the root complex and end point device go into a power-down state our device will, of course, follow that to achieve the lowest overall system power that's possible. Our retimers support either independent clocks or a common spread spectrum clock. So you have multiple options in terms of clocking. Our devices also support hot swapping. And finally, the retimers offer built-in instrumentation capabilities. There's a built in pattern generator and checker function, as well as an on-die scope capture capability. And this is very important. If you think back to that blade server application, where you have retimer parts on two blades at each end of the channel, from the transmitter side, you can now generate a pattern with the pattern generator function. That pattern can output a signal and you can adjust the output swing and emphasis characteristics, the slew rate. You've got full control over the output characteristics. Now that signal will then pass down the channel to the receiver. Now if the receiver is our retimer you have the ability to capture the input waveform either at the pin or after equalization. And of course, you can adjust your receiver characteristics, as well, input equalization as well as input sensitivity. So now you have the ability to margin your channel to provide optimum margins for operation. Of course PCI Express Gen3 can do that all automatically. As part of this instrumentation feature, you can output the data to a Windows based PC and look at it under a GUI, a user interface that IDT also provides. So it's software accessible. Being software accessible means it's very convenient to debug within the lab but also once the system is deployed within the field you could conceivably even access the information remotely, via the internet. So a very powerful tool with very powerful capabilities built into this retimer. 
 
To wrap up the advantages that IDT brings in terms of signal conditioning products, we have best in class analog performance, and this is hereditary. It's based on our experience with building high-speed memory buffers, the physical layout interface of those, built on our experience with PCI switching and SRIO switching and other devices. So we have excellent skills in the analog domain. We also consider these devices to be server-class or server-grade signal conditioning devices. And by that we mean that they have a lot of configuration capabilities, including the ability for automatic training under PCI Express Gen3. We wrap around our semi-conductor products a full suite of hardware development tools. I'd already mentioned the GUI that we have available. We have the instrumentation capabilities in these devices to make debug and design easy. And, finally, we have an excellent support team for our Signal Integrity products. The engineers are skilled in the unique requirements around signal conditioning and the unique problems that they present within your system. 
 
So I'd like to conclude on that note, and thank you for your time and attention.