The 8305-02 is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The 8305-02 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. Guaranteed output and part-to-part skew characteristics make the 8305-02 ideal for those applications demanding well defined performance and repeatability.
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Pkg. Type |
Lead Count (#) |
Temp. Grade |
Pb (Lead) Free |
Carrier Type |
ご購入 / サンプル |
|
---|---|---|---|---|---|---|
型名 | ||||||
TSSOP | 16 | C | Yes | Tube | ||
TSSOP | 16 | C | Yes | Reel |