概要

Not recommended for new designs

 

  • Higher drive than the 95V857 series devices 
  • Low skew, low jitter PLL clock driver 
  • 1 to 10 differential clock distribution (SSTL_2) 
  • Feedback pins for input to output synchronization 
  • PD# for power management 
  • Spread Spectrum-tolerant inputs 
  • Auto PD when input signal removed

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    95V2F857AGLF
    circle廃止品
    memory
    view_in_ar
    		TSSOP 48 C Yes Tube
    95V2F857AGLFT
    circle廃止品
    memory
    view_in_ar
    		TSSOP 48 C Yes Reel
    95V2F857AHLF
    circle廃止品
    memory
    view_in_ar
    		CABGA 56 C Yes Tray
    95V2F857AHLFT
    circle廃止品
    memory
    view_in_ar
    		CABGA 56 C Yes Reel
    95V2F857AKLF
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 40 C Yes Tray
    95V2F857AKLFT
    circle廃止品
    memory
    view_in_ar
    		VFQFPN 40 C Yes Reel
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