概要

DDR Zero Delay Clock Buffer

  • Low skew, low jitter PLL clock driver
  • Max frequency supported = 266MHz (DDR 533)
  • I2C for functional and output control
  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • 3.3V tolerant CLK_INT input

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    93732AFLF
    circle廃止品
    memory
    view_in_ar
    		SSOP 28 C Yes Tube
    93732AFLFT
    circle廃止品
    memory
    view_in_ar
    		SSOP 28 C Yes Reel
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