概要

The 180-52 generates a low EMI output clock from a clock or crystal input. The device uses IDT's proprietary mix of analog and digital Phase-Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. The 180-52 offers center spread selection of +/-0.625% and +/-1.875%. Refer to the MK1714-01/02 for the widest selection of input frequencies and multipliers. IDT offers a complete line of EMI reducing clock generators. Consult us when you need to remove crystals and oscillators from your board.
180-52 - Block Diagram
180-52 - Block Diagram
  • Pin and function compatible to Cypress W180-52
  • Packaged in 8-pin SOIC
  • Provides a spread spectrum output clock
  • Accepts a clock input and provides same frequency dithered output
  • Input frequency of 8 to 15 MHz
  • Peak reduction by 7dB - 14dB typical on 3rd - 19th odd harmonics
  • Spread percentage selection for +/-0.625% and +/-1.875%
  • Operating voltage of 3.3 V and 5 V
  • Advanced, low-power CMOS process

ドキュメント

= ピックアップ
分類 タイトル 日時
データシート
180-52 Datasheet
PDF 208 KB
EOL通知
PDN# : U-13-05R2 PRODUCT DISCONTINUANCE NOTICE (REVISED)
PDF 161 KB
製品変更通知
PCN# : A1309-01 Changed of Traceability Mark Format
PDF 439 KB
EOL通知
PDN# : U-13-05R1 PRODUCT DISCONTINUANCE NOTICE
PDF 161 KB
EOL通知
PDN# : U-13-05 PRODUCT DISCONTINUANCE NOTICE
PDF 159 KB
製品変更通知
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products
PDF 361 KB
製品変更通知
PCN# A-0607-06 MMT Thailand as Alternate Assembly Facility for PLCC, SOIC 150mil/300mil
PDF 223 KB
7 items

設計・開発

ECADモデル

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Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    180M-52LF
    circle廃止品
    memory
    view_in_ar
    		SOIC 8 C Yes Tube
    180M-52LFT
    circle廃止品
    memory
    view_in_ar
    		SOIC 8 C Yes Reel
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