Overview

Description

The ISL6364 is a dual PWM controller; its 4-phase PWMs control the microprocessor core or the memory voltage regulator, while its single-phase PWM controls the peripheral voltage regulator for graphics, system agent, or processor I/O. The ISL6364 utilizes Renesas' proprietary Enhanced Active Pulse Positioning (EAPP) modulation scheme to achieve extremely fast transient response with fewer output capacitors. The ISL6364 is designed to be compliant to Intel VR12/IMVP7 specifications. It accurately monitors the load current via the IMON pin and reports this information via the IOUT register to the microprocessor, which sends a PSI# signal to the controller at low power mode via SVID bus. The controller enters 1 or 2-phase operation in low power mode (PSI1); in the ultra-low power mode (PSI2, 3), it operates in single phase with diode emulation option. In low power modes, the magnetic core and switching losses are significantly reduced, yielding high efficiency at light load. After the PSI# signal is de-asserted, the dropped phase(s) are added back to sustain heavy load transient response and efficiency. today's microprocessors require a tightly regulated output voltage position versus load current (droop). The ISL6364 senses the output current continuously by measuring the voltage across a dedicated current sense resistor or the DCR of the output inductor. The sensed current flows out of the FB pin to develop a precision voltage drop across the feedback resistor for droop control. Current sensing also provides information for channel current balancing, average overcurrent protection and individual phase current limiting. The TM and TMS pins sense an NTC thermistor's temperature, which is internally digitized for thermal monitoring and for integrated thermal compensation of the current sense elements of the respective regulator. The ISL6364 features remote voltage sensing and completely eliminates any potential difference between remote and local grounds. This improves regulation and protection accuracy. The threshold-sensitive enable input is available to accurately coordinate the start-up of the ISL6364 with other voltage rails.

Features

  • Intel VR12/IMVP7 Compliant
  • SerialVID with Programmable IMAX, TMAX, BOOT, ADDRESS OFFSET Registers
  • Intersil's Proprietary Enhanced Active Pulse Positioning (EAPP) Modulation Scheme (Patented)
  • Variable Frequency Control During Load Transients to Reduce Beat Frequency Oscillation
  • Linear Control with Evenly Distributed PWM Pulses for Better Phase Current Balance During Load Transients
  • Voltage Feed-Forward and Adjustable Ramp Options
  • High Frequency and PSI Compensation Options
  • Dual Outputs
  • Output 1 (VR0): 1 to 4-Phase for Core or Memory (Coupled Inductor Compatible)
  • Output 2 (VR1): Single Phase for Graphics, System Agent, or Processor I/O
  • Differential Remote Voltage Sensing
  • ±0.5% Closed-loop System Accuracy Over Load, Line and Temperature
  • Phase Doubler Compatibility (NOT Phase Dropping via PWM Lines)
  • Proprietary Active Phase Adding and Dropping with Diode Emulation Scheme For Enhanced Light Load Efficiency
  • Programmable Slew Rate of Fast Dynamic VID for VR0
  • Dynamic VID Compensation (DVS) for VR1 at No Droop
  • Droop and Diode Emulation Options
  • Programmable 1 or 2-Phase Operation in PSI1/2/3 Mode
  • Programmable Standard or Coupled-Inductor Operation
  • Precision Resistor or DCR Differential Current Sensing
  • Integrated Programmable Current Sense Resistors
  • Integrated Thermal Compensation
  • Accurate Load-Line (Droop) Programming
  • Accurate Channel-Current Balancing
  • Accurate Current Monitoring
  • Average Overcurrent Protection and Channel Current Limit With Internal Current Comparators
  • Precision Overcurrent Protection on IMON & IMONS Pins
  • Independent Oscillators, up to 1MHz Per Phase, for Cost, Efficiency, and Performance Optimization
  • Dual Thermal Monitoring and Thermal Compensation
  • Start-up Into Pre-Charged Load
  • Pb-Free (RoHS Compliant)

Comparison

Applications

Documentation

Design & Development

Models