The Dynamically Reconfigurable Processor (DRP) technology from Renesas is special purpose hardware built into selected RZ Series MPUs that dramatically accelerates image processing algorithms by as much as 10X, or more. It combines the high performance of hardware solutions with the flexibility and expansion capability of a CPU.

Learn more about RZ/A2M MPUs with DRP Technology

 

DRP Technology Advantages

Flexibility

  • The DRP can accelerate multiple algorithms in a single application and offload the main processor for specialized tasks
  • New configurations can be dynamically loaded into the DRP in as little as 1 ms

Programming

  • The DRP compiler inputs C language and outputs downloadable configuration code for the programmable data path hardware and state transition controller (STC)
  • Complex algorithms are broken down into smaller “contexts” implemented in the programmable data path hardware
  • The STC switches individual contexts into the hardware as processing proceeds, and changes the next required context in a single clock cycle (nanoseconds)
  • The result is “virtually expandable,” configurable data path processing hardware for implementing complex algorithms (time and space-multiplexing)

Extreme Efficiency

  • Time and space-multiplexing delivers higher performance and lower power than CPU, GPU, or DSP
  • Integrated SRAM reduces external memory accesses to increase performance and reduce power

Using DRP Technology

  • Renesas offers a comprehensive and expanding library of image processing functions
  • Customers can optionally work with approved design partners to develop custom libraries

 

Dynamic Reconfiguration and Loading to Support Multiple Complex Algorithms

Dynamic Reconfiguration

  • The DRP can switch between multiple data paths (“contexts”) on each DRP clock cycle
  • Context switching is managed by the state transition controller (STC), and context loading is operated by the integrated DMAC.
  • "Time and space-multiplexing" can execute complex algorithms with fixed DRP area without hardware area expansion.


Dynamic Loading

  • The DRP can accelerate multiple, different algorithms in your application
  • Completely new configurations can be loaded into the DRP in as little as 1 millisecond
  • Dynamic loading can realize implementation of additional features without hardware revision during operation

DRP Accelerates Embedded Artificial Intelligence (e-AI)

  • The DRP speeds image pre-processing and reduces data size for AI inference
  • The RZ/A2M MPU provides high-speed and low-power e-AI solutions by enabling hybrid e-AI systems with DRP and CPU
  • The roadmap for DRP technology enhances AI inference in embedded devices at the endpoint