High-end automotive microcontroller suitable for instrument cluster supporting basic or low-level 2D drawing.

 

The RH850/D1M microcontroller has up to 5 MB embedded flash, 3.5 MB embedded RAM and dedicated features for instrument clusters with middle or high level 2D drawing. Therefore it integrates a 2D GPU, Sprite Engine, JPEG Unit, HUD Warping Engine and the RAM Wrapper. Furthermore it supports an external memory interface up to DDR2.

 

Main Solutions

Key Features:

 

 

176-pins / 272-pins

ITEM RH850/D1M
RH850/D1M1 RH850/D1M1-V2 RH850/D1M1H RH850/D1M1A
Pin Count 176-pin 272-pin
Part Name R7F701404
R7F701405
R7F701442 R7F701406
R7F701407
R7F701441
R7F701462 R7F701461
CPU CPU System RH850G3M
CPU Frequency 160 MHz 200 MHz 240 MHz
Memory Protection Unit (MPU) Supported
Floating Point Unit (FPU) Supported
Memory caches Instruction cache 8 KB / 4-way associative
Non-CPU s ystem memories 16 KB / 4-way associative
Memory Program Flash 3.75 MB (R7F701404) 4 MB 3.75 MB (R7F701406) 4 MB
5 MB (R7F701405)   5 MB
(R7F701407)
 
       
Data Flash 64 KB
Local RAM 512 KB
Retention RAM 16 KB
Video RAM with Video RAM wrapper 1.55 MB 2 × 1.55 MB
External memory interfaces SDRAM Interface Bus width - 32-bit
Mode - SDR-SDRAM (SDRA)
Max. clock - 100 MHz 120 MHz
Serial Flash Memory Interface
0
Bus width 8-bit
Mode SDR, DDR
Max. clock SDR : 120 MHz, DDR : 80 MHz
Serial Flash Memory Interface1 Bus width - 8-bit - 8-bit
Mode SDR, DDR SDR, DDR
Max. clock SDR,  DDR : 40 MHz SDR,  DDR : 40 MHz
Serial Flash Memory Interface2 Bus width - 4-bit
Mode SDR, DDR
Max. clock SDR,  DDR : 80 MHz
HyperBus
I/F
Bus width - 8-bit - 8-bit
Mode DDR DDR
Max. clock 80 MHz 80 MHz
OCTA
Flash I/F
Bus width - 8-bit - 8-bit
Mode DDR DDR
Max. clock 80 MHz 80 MHz
NAND
Flash I/F
Bus width - 8-bit
Mode ONFi 1.0 (mode 0 and 1)
DMA 16 channels
Operating clock Main Oscillator 8 to 16 MHz
Low Speed Internal Oscillator Typ. 240 kHz
High Speed Internal Oscillator Typ. 8 MHz
Sub Oscillator Typ. 32.768 kHz
Spread-spectrum PLL0 480 MHz 960 MHz 480 MHz 960 MHz
PLL1 Fixed to 480 MHz
PLL2 -
I/O port 126 127 126 127
A/D converter 16 channels, 12-bit resolution
Timer 16-bit Timer Array Unit B (TAUB) 3 units (16 channels / unit)
32-bit Timer Array Unit J (TAUJ) 1 unit (4 channels / unit)
Timer for Operating System (OSTM) 2 units (32-bit resolution, 1 channel / unit)
32-bit Always-On-Area Timer (AWOT) 1 unit (1 channel / unit)
Real Time Clock (RTCA) Supported
Window Watchdog Timer A (WDTA) 2 units
PWM Generators with Diagnostic 1 unit (12-bit resolution, 24 PWM generators, 12 with diagnostic capability)
Communication interface Clocked Serial Interface G (CSIG) 4 channels
Queued Clocked Serial Interface H (CSIH) 2 channels
CAN Interface
(RS-CAN)
3 channels (total 192 message buffers)
CAN Interface  (RSCANFD) - 3 channels (total 192 message buffers) - 3 channels (total 192 message buffers)
LIN / UART Interface (RLIN3) 4 channels
I2C Interface (RIIC) 2 channels
Ethernet AVB MAC (ETNB) 1 channel (Media Access Controller for up to 100 Mbps, with Audio Video Bridging)
Media Local Bus (MLBB) -
External interrupts Maskable 11
Non-maskable (NMI) 1 unit
Audio Sound Generator (SG) 5 units
PCM-PWM Converter (PCMP) 1 unit
I2S Interface (SSIF) 2 units (1 channel / unit)
Video and Graphics Video output (VO) Channels 1 channel (1024 x 1024 pixels, RGB888, 4 layers) 2 channels (1024 x 1024 pixels, RGB888, 4 layers)
Interface LVTTL: 30MHz LVTTL: 30MHz, SerialRGB: 40MHz LVTTL: 30MHz LVTTL: 48MHz(ch0), OpenLDI: 34MHz, VODDR: 30/10MHz(ch0/ch1),  SerialRGB: 40MHz(ch1)
Predistortion Warping Engine (VOWE) Warping Engine (VOWE) for video channel 0
RLE decoding Supported (Only for Background layer) Supported (All layers) Supported (Only for Background layer) Supported (All layers)
Sprite layer 3 x 16 sprites for 3 output layers 4 x 16 sprites for all layers 3 x 16 sprites for 3 output layers 4 x 16 sprites for all layers
Timing Controller (TCON) 7 programmable signals
Video input (VI) Channels 1 channel
Resolution 1024 x 1024 pixels
Pixel clock 30 MHz
Color formats RGB666, ITU656
Interface LVTTL
Graphics Processing Unit 2D Graphics Processing Unit (GPU2D), 80 MHz operation clock 2D Graphics Processing Unit (GPU2D), 100 MHz operation clock 2D Graphics Processing Unit (GPU2D), 120 MHz operation clock
JPEG Unit (JCUA) Supported
Video output data control Video Output Checker (VOCA) 2 CRC checker (DISCOM) Video Output Checker (VOCA) 2 CRC checker (DISCOM) for each video channel
Other functions LCD Bus Interface (LCBI) 18 bit output, max. 10 MHz -
Clock Monitors (CLMA) For Main oscillator, Low speed internal oscillator, High speed internal oscillator, PLL0, PLL1, Video Input pixel clocks
Data CRC (DCRA) Supported
Power-On-Clear (POC) Supported
Intelligent Stepper Motor Driver (ISM), incl. zero point detection for each channel 1 unit, 6 channels
Error Correction Coding (ECC) For Code Flash, Data Flash, Local RAM, Retention RAM, Video RAM, RS-CAN RAM, Caches tag / data RAMs
Intelligent Cryptographic Unit (ICU-S2) Supported
On-Chip Debug (OCD) Supported
Boundary Scan Supported
Voltage supply Internal logic Always-On-Area 3.3 V, 5 V via on-chip voltage regulator
Isolated-Area 3.3 V via on-chip voltage regulator
I/O buffers GPIO 3.3 V, 5 V
SDR- SDRAM - 3.3 V
DDR2-SDRAM -
Serial Flash Memory Interface0, 2 3.3 V
RSDS -
MIPI CSI-2 -
OpenLDI - 3.3 V
A/D Converter supplies 3.3 V, 5 V
Package HLQFP 24 x 24
(0.5 mm)
LQFP 24 x 24
(0.5 mm)
BGA 21 x 21
(1.0 mm)

 

376-pins / 484-pins

ITEM RH850/D1M
RH850/D1M2 RH850/D1M2H
Pin Count 376-pins 484-pins
Part Name R7F701408 R7F701428 R7F701410 R7F701430 R7F701411 R7F701431 R7F701412 R7F701432
CPU CPU System RH850G3M
CPU Frequency 240 MHz
Memory Protection Unit (MPU) Supported
Floating Point Unit (FPU) Supported
Memory caches Instruction cache 8 KB / 4-way associative
Non-CPU system memories 32 KB / 4-way associative
Memory Program Flash 3.75 MB (R7F701408, R7F701428) 5 MB (R7F701410, R7F701430) 3.75 MB (R7F701411, R7F701431) 5 MB (R7F701412, R7F701432)
Data Flash 64 KB
Local RAM 512 KB
Retention RAM 16 KB
Video RAM with VideoRAM wrapper 2 x 1.55 MB
External memory interfaces SDRAM Interface Bus width 16-bit 32-bit
Mode DDR2-SDRAM Interface (SDRB)
Max. clock 240 MHz
Serial Flash Memory Interface
0
Bus width 8-bit
Mode SDR, DDR
Max. clock SDR : 120 MHz, DDR : 80 MHz
DMA 16 channels
Operating clock Main Oscillator 8 to 16 MHz
Low Speed Internal Oscillator Typ. 240 kHz
High Speed Internal Oscillator Typ. 8 MHz
Sub Oscillator Typ. 32.768 kHz
Spread-spectrum PLL0 480 MHz
PLL1 Fixed to 480 MHz
PLL2 Up to 480 MHz
I/O port 159 199
A/D converter 20 channels, 12-bit resolution
Timer 16-bit Timer Array Unit B (TAUB) 3 units (16 channels / unit)
32-bit Timer Array Unit J (TAUJ) 1 unit (4 channels / unit)
Timer for Operating System (OSTM) 2 units (32-bit resolution, 1 channel / unit)
32-bit Always-On-Area Timer (AWOT) 1 unit (1channels / unit)
Real Time Clock (RTCA) Supported
Window Watchdog Timer A (WDTA) 2 units
PWM Generators with Diagnostic 1 unit (12-bit resolution, 24 PWM generators, 12 with diagnostic capability)
Communication interface Clocked Serial Interface G (CSIG) 4 channels
Queued Clocked Serial Interface H (CSIH) 2 channels
CAN Interface
(RS-CAN)
3 channels (total 192 message buffers)
CAN Interface  (RSCANFD) 3 channels (total 192 message buffers)
LIN / UART Interface (RLIN3) 4 channels
I2C Interface (RIIC) 2 channels
Ethernet AVB MAC (ETNB) 1 channel (Media Access Controller for up to 100 Mbps, with Audio Video Bridging)
Media Local Bus (MLBB) - 1 channel (50 Mbps)
External interrupts Maskable 11
Non-maskable (NMI) 1
Audio Sound Generator (SG) 5 units
PCM-PWM Converter (PCMP) 1 unit
I2S Interface (SSIF) 2 units (1 channel / unit)
Video and Graphics Video output (VO) Channels 2 channels (1280 x 1024 pixels, RGB888, 4 layers)
Interface LVTTL for both channels: 48 MHz, RSDS selectable for channel 0 or 1: 48 MHz
Predistortion Warping Engine (VOWE) for video channel 0
RLE decoding Supported (Only for Background layer)
Sprite layer 3 x 16 sprites for 3 output layers
Timing Controller (TCON) 7 programmable signals
Video input (VI) Channels 1 channel 2 channels
Resolution 1024 x 1024 pixels
Pixel clock 60 MHz
Color formats RGB888, ITU656
Interface LVTTL for both channels, single MIPI CSI-2 for channel 0
Graphics Processing Unit 2D Graphics Processing Unit (GPU2D), 240 MHz operation clock
JPEG Unit (JCUA) Supported
Video output data control Video Output Checker (VOCA) , 2 CRC checker (DISCOM) for each video channel
Other functions LCD Bus Interface (LCBI) -
Clock Monitors (CLMA) For Main oscillator, Low speed internal oscillator, High speed internal oscillator, PLL0, PLL1, Video Input pixel clocks
Data CRC (DCRA) Supported
Power-On-Clear (POC) Supported
Intelligent Stepper Motor Driver (ISM), incl. zero point detection for each channel 1 unit, 4 channels 1 unit, 6 channels
Error Correction Coding (ECC) For Code Flash, Data Flash, Local RAM, Retention RAM, Video RAM, RS-CAN RAM, Caches tag / data RAMs
Intelligent Cryptographic Unit (ICU-S2) Supported
On-Chip Debug (OCD) Supported
Boundary Scan Supported
Voltage supply Internal logic Always-On-Area 3.3 V, 5 V via on-chip voltage regulator
Isolated- Area 1.25 V
I/O buffers GPIO 3.3 V, 5 V
SDR- SDRAM -
DDR2- SDRAM 1.8 V
Serial Flash Memory Interface0, 2 3.3 V
RSDS - 3.3 V
MIPI CSI-2 - 3.3 V
OpenLDI
A/D Converter supplies 3.3 V, 5 V
Package BGA 23 x 23 BGA 27 x 27
(1.0 mm) (1.0 mm)

Pin Count / Memory Size Lineup:

Program Flash
SRAM

5MB
512KB
 
4MB
512KB
     
3.75MB
512KB
 
Pins
Package
176
HLQFP
176
LQFP
272
BGA
376
BGA
484
BGA

 

Block Diagram:

RH850/D1M Block Diagram

You can find an explanation of orderable part numbers here.

 

Resources for Software and Hardware

Title Description
My Renesas Create a My Renesas account to use our tool download services, receive e-newsletter/update notifications, and take advantage of our other services.
e-learning Information for studying and learning about microcontrollers and microprocessors.
FAQ Frequently asked questions and useful hints for development.
Forum A forum and community site to share technical information, questions and opinions with others who use Renesas products.

 

Software Design Support

Title Description
CS+ An integrated development environment that can be used for coding, assembling/compiling, and simulation. (Also included with Renesas Starter Kits.)
e2 studio Renesas eclipse embedded studio, known as e² studio, is a complete development and debug environment based on the popular Eclipse CDT project.
E1 A standard Renesas on-chip debugging emulator that enables users to carry out ample debugging for real development at low cost. (Also included with starter kits.)

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