These microcontrollers employ the RL78 core which realizes high processing performance while delivering the lowest power consumption in their class, and have enhanced computing power and peripheral functions suitable for motor control and other applications.

In addition to a high-precision (±2%) on-chip oscillator enabling 24 MHz CPU operation and other standard on-chip functions from the RL78/G13, these microcontrollers have multiply and divide and multiply-accumulate instructions capability, and functions from the R8C Family with proven track records, such as timers RD/RJ, event link controller,  and 1ch of programmable gain amplifier, 2ch of comparator helping to lower the total cost of building a system and contributing to more compact size and lower power consumption.

Pin Count / Memory Size Lineup

R7F0C008/009-Pin Count / Memory Size Lineup

Block Diagram

Key Features

  • Minimum instruction execution time can be changed from high speed (0.04167 μs: @ 24 MHz operation with high-speed on-chip oscillator clock) to low-speed (1.0 μs: @ 1 MHz operation with high-speed on-chip oscillator clock)
  • General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
  • ROM: 8 to 16 KB, RAM: 1.5 KB
  • High-speed on-chip oscillator clocks
    • Selectable from 48 MHz (TYP.), 24 MHz (TYP.), 16 MHz (TYP.), 12 MHz (TYP.), 8 MHz (TYP.), 4 MHz (TYP.), and 1 MHz (TYP.)
  • On-chip single-power-supply flash memory (with prohibition of block erase/writing function)
  • Self-programming (with flash shield window function)
  • On-chip debug function
  • On-chip power-on-reset (POR) circuit and voltage detector (LVD)
  • On-chip watchdog timer (operable with the dedicated low-speed on-chip oscillator clock)
  • Multiply/divide/multiply & accumulate instructions are supported
  • On-chip key interrupt function
  • On-chip clock output/buzzer output controller
  • On-chip BCD adjustment
  • I/O ports: 26 to 40
  • Timer
    • 16-bit timer: 7 channels
      (TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels)
    • Watchdog timer: 1 channel
      12-bit interval timer: 1 channel
  • Serial interface
    • CSI
    • UART
    • Simplified I2C
  • Different potential interface: Can connect to a 2.5/3 V device when operating at 4.0 V to 5.5 V
  • 8/10-bit resolution A/D converter (VDD = 2.7 to 5.5 V): 8 to 12 channels
  • Standby function: HALT, STOP, SNOOZE mode
  • On-chip comparator
  • On-chip programmable gain amplifier
  • On-chip event link controller (ELC)
  • Power supply voltage: VDD = 2.7 to 5.5 V
  • Operating ambient temperature: TA = -40 to +85 °C
    Remark The functions mounted depend on the product. See Hardware Manual section 1.6 Out of Functions.
  • ROM, RAM capacities
Flash ROM RAM R7F0C008A/B/F, R7F0C009A/B/F
30 pins 32 pins
44 pins
16 KB 1.5KB Note R7F0C009A2DSP R7F0C009B2DFP R7F0C009F2DFP
8 KB R7F0C008A2DSP R7F0C008B2DFP R7F0C008F2DFP

Note: This is 630 bytes when the self-programming function is used. (For details, see CHAPTER 3 CPU ARCHITECTURE).

Outline of Functions

30-pin, 32-pin, 44-pin products (code flash memory 8 KB to 16 KB)

Caution     The above outline of the functions applies when peripheral I/O redirection register 1 (PIOR1) is set to 00H.

Item
30 pins 32 pins 44 pins
R7F0C008A2,R7F0C009A2 R7F0C008B2, R7F0C009B2 R7F0C008F2, R7F0C009F2
Code flash memory
8 to 16 KB
RAM 1.5 KB
Address space 1 MB
Main system clock
High-speed system clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V
High-speed on-chip oscillator clock (fIH) HS (high-speed main) mode: 1 to 24 MHz (VDD = 2.7 to 5.5 V)
Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 2.7 to 5.5 V
General-purpose register 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time 0.04167μs (High-speed on-chip oscillator clock: fIH = 24 MHz operation)
0.05μs (High-speed system clock: fMX = 20 MHz operation)
Instruction set Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
Multiplication and Accumulation (16 bits × 16 bits + 32 bits)Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc
I/O port Total 26 28 40
CMOS I/O 23 25 35
CMOS input 3 3 5
CMOS output -
N-ch open-drain I/O
(6 V tolerance)
-
Timer 16-bit timer
7 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels)
Watchdog timer 1 channel
12-bit interval timer
1 channel
Timer output
14
(TAU: 4, Timer RJ: 2, Timer RD: 8)
PWM outputs: 9 (TAU: 3, Timer RD: 6_
Clock output/buzzer output 2
2.44kHz, 4.88kHz, 9.76kHz, 1.25MHz, 2.5MHz, 5MHz, 10MHz
(Main system clock: fMAIN = 20 MHz operation)
8/10-bit resolution A/D converter 8 channels 12 channels
Serial interface CSI: 1 channel/UART0: 1 channel/simplified I2C: 1 channel
UART1: 1 channel
Event link controller (ELC) Event input: 18
Event trigger output: 6
Event input: 19
Event trigger output: 6
Vectored interrupt sources Internal 20
External 6 7
Key interrupt - 4
Reset Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction executionNote
Internal reset by RAM parity error
Internal reset by illegal-memory access
Power-on-reset circuit Power-on-reset: 1.51 ±0.03 V
Power-down-reset: 1.50 ±0.03V
Voltage detector 2.75 V to 4.06 V (6 stages)
On-chip debug function Priovided
Power supply voltage VDD= 2.7 to 5.5V
工Operating ambient temperature TA= – 40 to +85°C

Caution: Since a library is used when rewriting the flash memory using the user program, flash ROM and RAM areas are used. Refer to the RL78 Family Flash Self-Programming Library Type01 User’s Manual before using these products.

Note: The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug emulator.

Key Applications

Small motor control, IH cooker.

Product Lineup

Document Part No Program Memory
(KB)
RAM
(KB)
Operating Voltage min
(V)
Package Code Production Packing / Lead Free Order Part No
Chinese English
PDF PDF R7F0C008A2DSP 8 1.5 2.7 PLSP0030JB-B
30-pin plastic
SSOP(6.1x9.85)
Mass Production Tray / Lead free
(Pure Sn)
R7F0C008A2DSP#AA0
R7F0C008A2DSP Embossed Tape/ Lead free
(Pure Sn)
R7F0C008A2DSP#HA0
R7F0C008B2DSP-C PLQP0032GB-A
32-pin plastic
LQFP(7x7)
Tray / Lead free
(Pure Sn)
R7F0C008B2DFP-C#AA0
R7F0C008B2DSP-C Embossed Tape/ Lead free
(Pure Sn)
R7F0C008B2DFP-C#HA0
R7F0C008F2DFP-C PLQP0044GC-A
44-pin plastic
LQFP(10x10)
Tray / Lead free
(Pure Sn)
R7F0C008F2DFP-C#AA0
R7F0C008F2DSP-C Embossed Tape/ Lead free
(Pure Sn)
R7F0C008F2DFP-C#HA0
R7F0C009A2DSP 16 PLSP0030JB-B
30-pin plastic
SSOP(6.1x9.85)
Tray / Lead free
(Pure Sn)
R7F0C009A2DSP#AA0
R7F0C009A2DSP Embossed Tape/ Lead free
(Pure Sn)
R7F0C009A2DSP#HA0
R7F0C009B2DSP-C PLQP0032GB-A
32-pin plastic
LQFP(7x7)
Tray / Lead free
(Pure Sn)
R7F0C009B2DFP-C#AA0
R7F0C009B2DSP-C Embossed Tape/ Lead free
(Pure Sn)
R7F0C009B2DFP-C#HA0
R7F0C009F2DFP-C PLQP0044GC-A
44-pin plastic
LQFP(10x10)
Tray / Lead free
(Pure Sn)
R7F0C009F2DFP-C#AA0
R7F0C009F2DSP-C Embossed Tape/ Lead free
(Pure Sn)
R7F0C009F2DFP-C#HA0
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