The 72T36135M is a 512K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a wide extended x 36 bus to allow ample data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data at very high performance. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.


  • Functionally and pin compatible to 9Mbit 72T36125
  • User selectable HSTL/LVTTL Input and/or Output
  • User selectable Asynchronous read and/or write port timing
  • Program programmable flags by either serial or parallel means
  • Auto power down minimizes standby power consumption
  • Master Reset clears entire FIFO
  • Partial Reset clears data, but retains programmable settings
  • Empty and Full flags signal FIFO status
  • Output enable puts data outputs into high impedance state
  • JTAG port, provided for Boundary Scan function
  • Available in 240-pin PBGA package
  • Independent Read and Write Clocks (permit reading and writing simultaneously)
  • Industrial temperature range (–40C to +85C) is available

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active PBGA 240 C No Tray
Active PBGA 240 C Yes Tray
Active PBGA 240 C No Tray
Active PBGA 240 I No Tray

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
72T36135M Datasheet Datasheet PDF 630 KB
User Guides & Manuals
Cypress Discontinued Dual-port and FIFO to IDT Cross Reference Guide Guide PDF 123 KB
PCN# A-0605-07 Transfer 144, 240, 260, 324L PBGA from ATK to ATP Product Change Notice PDF 99 KB
PCN#: TB-0512-01 Reel Color Changed from Blue to Black Product Change Notice PDF 729 KB
72T36135M BSDL Model - BSDL ZIP 101 KB
idt72T36135M.verilog.5.tar Model - Verilog ZIP 106 KB
72T36135M IBIS Model - IBIS ZIP 19 KB