The RMHE41A184AGBG is a 67, 108, 864-word by 18-bit and the RMHE41A364AGBG is a 33, 554, 432-word by 36-bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using DRAM memory cell. The Low Latency DRAM-III chip is a 1. 1Gb DRAM capable of a sustained throughput of approximately 57. 6 Gbps for burst length of 4 (approximately 51. 2 Gbps for applications implementing error correction), excluding refresh overhead and data bus turn-around With a bus speed of 800 MHz, a burst length of 4, and a tRC of 13. 75 ns, the Low Latency DRAM-III chip is capable of achieving this rate when accesses to at least 6 banks of memory are overlapped. These products are packaged in 180-pin FCBGA.
- 2 cycle 800MHz DDR Muxed Address
- Optional data bus inversion to reduce SSO, SSN, maximum I/O current, and average I/O power
- Training sequence for per-bit deskew
- Selectable Refresh Mode: Auto or Overlapped Refresh
- Programmable PVT-compensated output impedance
- Programmable PVT-compensated on-die input termination
- PLL for improved input jitter tolerance and wide output data valid window