IP List is separated by Processor, Memory, Interface, Digital and Analog as follows

Processor IPs

Function IP name Process
(or Soft macro)
Status Document Inquiry
CPU subsystem RX
32-bit CISC CPU for high computing performance and excellent low power consumption.
Soft macro Coming soon - Contact
SH-4A
32-bit RISC (reduced instruction set computer) microprocessor, featuring object code upward-compatibility with Renesas SuperH SH-1, SH-2, SH-3, and SH-4 microcomputers.
Soft macro Available Datasheet
SH-4
32-bit RISC (reduced instruction set computer) microprocessor, featuring object code upward-compatibility with Renesas SuperH SH-1, SH-2, SH-3, and SH-3E microcomputers.
Soft macro Available Datasheet
SH3-DSP
Compatible with object code level with SH-1, SH-2, and SH-3
For multiply instructions and DSP arithmetic instructions
Soft macro Available Datasheet
SH-2A
High performance 32-bit RISC CPU with two instructions running simultaneously.
Soft macro Available Datasheet
SH2-DSP
The SH2-DSP CPU interprets and executes the SH-DSP instruction that extended the SH 2 instruction.
For multiply instructions and DSP arithmetic instructions, calculations are performed with a digital signal processor (DSP) module.
Soft macro Available Datasheet
H8S
Command compatible upper order with H8 / 300, H8 / 300H.
CPU H8S C200 package includes BSC, INTC, Timer, WDT, SCI peripheral modules.
Soft macro Available Datasheet
M32R
Two formats of 16 bit length instruction and 32 bit instruction are adopted.
Multiply-accumulate function
SRAM, cache, bus control circuit, interrupt controller, multifunction timer, serial I/O, watchdog timer as peripherals
Soft macro Available Datasheet

Digital IPs

Function IP name Process
(or Soft macro)
Status Document Inquiry
Timer GPT
General PWM timer (GPTA) consisting of a four-channel 16-bit timer.
Soft macro Available Datasheet Contact
TPU
On-chip 16-bit timer pulse units (TPU) comprising six-channel 16-bit timers.
Soft macro Available Datasheet
WDT
The watchdog timer (WDT) is a 14-bit down-counter. It can be used to reset the system when the counter underflows because its value cannot be refreshed due to the system being out of control.
Soft macro Available Datasheet
Peripheral CAN
Three channels of the CAN (Controller Area Network) module that complies with the ISO 11898-1 Standards.
Transmits and receives both formats of messages, namely the standard identifier (11-bits) (identifier is hereafter referred to as ID) and extended ID (29-bits).
Soft macro Available Datasheet Contact
SPI
Two channels of Serial Peripheral Interface (RSPI).
Capable of high-speed, full-duplex synchronous serial communications with multiple processors and peripheral devices.
Soft macro Available Datasheet
I2C
Two channels I2C-bus interface (RIIC0, RIIC2).
Conforms with the NXP I2C-bus (Inter-IC bus) interface and provides a subset of its functions.
Soft macro Available Datasheet
SCI
Nine independent serial communications interface (SCI) channels.
Consists of the SCIg module (SCI0 to SCI7) and the SCIh module (SCI12).
Soft macro Available Datasheet
EthrtnetAVB
provides interface features for End Station in Ethernet Audio Video Bridging networks.
Ethernet controller that conforms to the definition of the MAC layer for Ethernet in the IEEE 802.3 standard.
Include dedicated direct memory access controller for transferring transmitted Ethernet frames to and received Ethernet frames from respective storage areas in the memory at high speed.
Soft macro Available Datasheet

Memory IPs

Some IPs below are contracted design. Please contact us for detail.

Function IP name Process
(or Soft macro)
Status Document Inquiry
Flash MONOS eFlash
Expand to not only MCU also many applications of SoC field.
Programming/erasing as background operations (BGOs)
Supports versions with up to 4 MB of ROM as Code Flash
64 KB, reprogrammable up to 250,000 times as Data Flash
TSMC 40nm Available Datasheet Contact
SRAM, TCAM 1WR,1W1R(2clk,1clk),2WR(2clk,1clk),2W2R(1clk),TCAM
By optimizing the peripheral circuit of memory, particularly small area is realized.
Support low leak retention mode (Resume Standby) and power off mode (Shut down).
TSMC(40nm,28nm,16nm,12nm) Available Datasheet

Interface IPs

Some IPs below are contracted design. Please contact us for detail.

Function IP name Process
(or Soft macro)
Status Document Inquiry
PCIe/USB/SATA PHY Combo Serdes PHY
Useful analog transceiver hard macro for various high speed serial interface PHY layer.
Designed for PCI Express 2.1 / USB3.0 SuperSpeed / Serial ATA Revision 3.1 and can be used for each interface as "Combo" without GDS replace.
TSMC 28nm Available Datasheet Contact
Combo PHY
Based on the PHY Interface for the PCI Express, USB3.0 Architecture Version 3.00 and Serial ATA Revision 3.1 .
Including Combo Serdes PHY.
TSMC 28nm Available Datasheet
SerDes PHY upto 10Gbps(PCIe gen3, 10GKR, SATA3)
Useful analog transceiver hard macro for various high speed serial interface PHY layer.
Used as 1.25 to 16 Gbps various high speed interface standards PHY.
Soft & TSMC 28nm Coming soon Datasheet
SerDes PHY upto 16Gbps(PCIe gen4, 10GKR, SATA3)
Useful analog transceiver hard macro for various high speed serial interface PHY layer.
Used as 1.25 to 16 Gbps various high speed interface standards PHY.
Soft & TSMC 28nm Coming soon Datasheet
PCIe2/USB3SS Combo PHY (SandyMLS+ 5GSerDes PHY)
Useful analog transceiver hard macro for various high speed serial interface PHY layer.
Designed for PCI Express 2.1 / USB3.0 SuperSpeed.
TSMC 28nm Available Datasheet
SATA3 PHY (SandyMLS+ 6GSerDes PHY)
Useful analog transceiver hard macro for various high speed serial interface PHY layer.
Designed for Serial ATA Revision 3.1.
TSMC 28nm Available Datasheet
PCIe2/USB3SS Combo PHY (SandyMLSu+ 5GSerDes PHY)
Useful analog transceiver hard macro for various high speed serial interface PHY layer.
Designed for PCI Express 2.1 / USB3.0 SuperSpeed.
Coming soon Coming soon -
SATA3 PHY (SandyMLSu+ 6GSerDes PHY)
Useful analog transceiver hard macro for various high speed serial interface PHY layer.
Designed for Serial ATA Revision 3.1.
Coming soon Coming soon -
USB2.0 MultiPort PHY:UTMI+Level3 Multiport Tranceiver
Useful analog Multi port transceiver hard macro for UTMI (USB2.0 Transceiver Marco cell Interface) + Level3
Configured to operate as a USB2.0 peripheral or USB2.0 host controller.
TSMC 28nm Available Datasheet
USB2.0 MultiPort PHY:UTMI+Level3 Multiport Tranceiver
Useful analog Multi port transceiver hard macro for UTMI (USB2.0 Transceiver Marco cell Interface) + Level3
Configured to operate as a USB2.0 peripheral or USB2.0 host controller.
Coming soon Coming soon -
USB2.0 PHY:UTMI+Level3 Tranceiver
Useful analog 1 port transceiver hard macro for UTMI (USB2.0 Transceiver Marco cell Interface) + Level3
Configured to operate as a USB2.0 peripheral or USB2.0 host controller.
TSMC 40nm Available Datasheet
USB LINK USB3.1 (Gen1) xHCI Host Controller
Compliant with the Universal Serial Bus (USB) 3.1 Specification.
Supports USB3.1 bus-speeds: Super Speed (5 Gbps), High Speed (480 Mbps), Full Speed (12Mbps), and Low Speed (1.5Mbps).
Compliant with the Battery Charging Specification Revision 1.2, and is based on the eXtensible Host Controller Interface for the Universal Serial Bus (xHCI) Specification as a Host Controller Interface.
Soft macro Available Datasheet Contact
USB3.1 (Gen1) Peripheral Controller
Compliant with the Universal Serial Bus (USB) 3.1 Specification and enables connectivity to USB3.1 system with proven design experiences.
Contains Endpoint Controller and has AXI bus bridge.
Supports Super Speed (5 Gbps), High Speed (480 Mbps) and Full Speed (12Mbps).
Soft macro Available Datasheet
USB2.0 EHCI Host Controller
Compliant with the Universal Serial Bus (USB) 2.0 Specification and Enhanced Host Controller Interface(EHCI) Specification.
Based on the proven controller uPD720102 adopted many products around the world.
Soft macro Available Datasheet
USB2.0 On-The-Go (OTG) Controller
Compliant with the Universal Serial Bus (USB) 2.0 Specification, Enhanced Host Controller Interface(EHCI) Specification, and On-The-Go Supplement Specification.
Consists of the host controller "uu2hcabhutmi" and the peripheral controller "uu2pcahbutmi".
Soft macro Available Datasheet
USB2.0 Peripheral Controller
Compliant with the Universal Serial Bus (USB) 2.0 Specification.
Based on the proven controller R8A66597 adopted many products around the world.
Soft macro Available Datasheet
SATA LINK SATA3.2 Host Controller
Compliant with Serial ATA Rev.3.2 specification.
Supports Gen3 feature with Link/Transport Layer and PHY DIGITAL
Soft macro Available Datasheet Contact
MIPI MIPI D-PHY CSI (umipi_DC01L2V10_TOP)
Useful 2 Data Channel receiver hard macro for CSI2.
Soft & TSMC 40nm Coming soon - Contact
FPD_Link FPD_Link RX (ulvdsrx5chv10)
Useful 5 Data Channel LVDS Receiver and 1:7 SERIAL to PARALLEL Converting.
Soft & TSMC 28nm Coming soon Datasheet Contact
FPD_Link TX (AT28CLVD0003LVDSTX5CHLBT2_R0)
Useful 5 Channel LVDS Driver and 7:1 PARALLEL to SERIAL Converting.
Can be selected CLOCK Channel.
TSMC 28nm Coming soon Datasheet
V-by-One V-by-One HS Tx PHY
Useful analog transmitter hard macro for V-by-One® HS 1.4
TSMC 28nm Coming soon Datasheet Contact

Analog IPs & Data converter IPs

Some IPs below are contracted design. Please contact us for detail.

Function IP name Process
(or Soft macro)
Status Document Inquiry
Clock 4GHz Fractional PLL
Including Loop-filter
Input frequency range : 20 MHz to 200 MHz
Output frequency range : 62.5 MHz to 4000 MHz
TSMC 28nm Coming soon Datasheet Contact
1.8GHz SSCG PLL
Including Loop-filter.
Input frequency range : 12 MHz to 192 MHz
Output frequency range : 900 MHz to 1800 MHz
TSMC 28nm> Coming soon Datasheet
1.4GHz Deskew PLL
Including Loop-filter
Input frequency range : 12 MHz to 400 MHz
Output frequency range : 48 MHz to 1400 MHz
TSMC 28nm Coming soon Datasheet
1.7GHz Mulriplying PLL
Including Loop-filter
Input frequency range : 9.6 MHz to 216 MHz
Output frequency range : 850 MHz to 1700 MHz
TSMC 28nm Available Datasheet
5GHz Multiplying PLL
Including Loop-filter
Input frequency range : 12 MHz to 320 MHz
Output frequency range : 1250 MHz to 2500 MHz
TSMC 28nm Available Datasheet
1.8GHz SSCG PLL
Including Loop-filter.
Input frequency range : 12 MHz to 192 MHz
Output frequency range : 900 MHz to 1800 MHz
TSMC 28nm Available Datasheet
1.68GHz Deskew PLL
Including Loop-filter.
Input frequency range : 22.528 MHz to 420 MHz
Output frequency range : 45 MHz to 1680 MHz
TSMC 28nm Coming soon Datasheet
1.25GHz Multiplying PLL
Including Loop-filter.
Input frequency range : 9.6 MHz to 100 MHz
Output frequency range : 72.5 MHz to 1250 MHz
TSMC 40nm Coming soon Datasheet
1.056GHz SSCG PLL
Including Loop-filter.
Input frequency range : 10 MHz to 132 MHz
Output frequency range : 80 MHz to 1056 MHz
TSMC 40nm Coming soon Datasheet
Convertor 2 channels 12-bit R-2R DAC w/ buffer (3us)
Supporting the wide supply range from 1.62 to 3.63V.
TSMC 40nm Coming soon Datasheet Contact
2 channels 8-bit R-String DAC (2uA)
Supporting the wide supply range from 1.62 to 3.63V.
Novel architecture
TSMC 40nm Coming soon Datasheet
12-bit SAR ADC (1.8V, 0.5us)
Analog Input range : 0 to VCCA, single-ended.
14 channels analog inputs multiplexer included.
TSMC 28nm Available Datasheet
12-bit SAR ADC (1.8V, 0.5us)
Analog Input range : 0 to VCCA, single-ended.
14 channels analog inputs multiplexer included.
TSMC 28nm Available Datasheet
12-bit SAR ADC (3V, 0.4us)
Resolution : 12/10/8 bit selectable
Supply voltage: VCCA=2.7 to 3.6 V
TSMC 40nm Coming soon Datasheet
12-bit SAR ADC (3V, 0.4us)
Resolution : 12/10/8 bit selectable
Supply voltage: VCCA=2.7 to 3.6 V
TSMC 40nm Available Datasheet
Temp. Sensor, etc Temp. Sensor (with ADC)
Including ADC outputs a digital code which corresponds to the detected temperature of LSI.
TSMC 28nm Coming soon Datasheet Contact
Temp. Sensor (with analog output buffer)
Including Analog Buffer outputs a analog voltage which corresponds to the detected temperature of LSI.
TSMC 40nm Coming soon Datasheet
Temp. Sensor (with analog output buffer)
Including Analog Buffer outputs a analog voltage which corresponds to the detected temperature of LSI.
TSMC 40nm Available Datasheet
Voltage Detector (3ch)
Check power supply level operating at lower power supply voltage and low current consumption
The detection level can be selected from 1.52V to 3.72V at 45 steps.
TSMC 40nm Coming soon Datasheet
High Speed Comparator
Conversion time is 100ns at worst condition.
Contains 3 cells of Comparator, Bias and Control.
TSMC 40nm Coming soon Datasheet
Low Power Comparator
Contains 2 cells of comparator and bias.
Available window mode and single mode as comparison mode, and Low power mode and high speed mode as current consumption mode.
TSMC 40nm Coming soon Datasheet
OPAMP
Contains 2 cells of AMP and IREF. IREF cell can be connected upto 4 AMPs. The OPAMP has 3 current mode of High speed, middle speed and low power mode.
TSMC 40nm Coming soon Datasheet
Analog Switch w/ Gate Voltage Booster
Contains 3 cells of Charge Pump,500 ohm Switch and 2k ohm Switch.
To ensure the characteristics of the on-resistance at lower power supply voltage, output of the Charge Pumps are used as power supply for analog switches.
TSMC 40nm Coming soon Datasheet

Other IPs (I/O, Standard Cell, etc.)

Some IPs below are contracted design. Please contact us for detail.

Function IP name Process
(or Soft macro)
Status Document Inquiry
I/O GPIO for 16nm
The 1.8V general purpose I/O library.
3.3V/1.8V dual voltage IO with 1.8V device are provided.
TSMC 16nm Available Datasheet Contact
GPIO for 28nm
The 1.8V general purpose I/O library.
3.3V/1.8V dual voltage IO with 1.8V device are provided.
TSMC 28nm Available Datasheet
GPIO for 40nm
3.3V general purpose(GPIO) I/O library with over-drive 2.5V device.
5V tolerant IO and I2C are supported.
TSMC 40nm Available Datasheet
Standard cell 1.8V-Stdcell
Useful library for low leak macro.
Suitable for low-speed and low leak macro development.
TSMC 28nm Available Datasheet Contact
3.3V-Stdcell
Useful library for low leak macro.
Suitable for low-speed and low leak macro development.
TSMC 40nm Available Datasheet

Model Based Development (MBD)

Function IP name Status Document Inquiry
MCU IP MILS model HEV/EV Motor Control IP Model (RH850/C1M-A Motor Control IP(EMU3), Motor Timer IP(TSG3)) Available Datasheet Contact
MBD Performance Estimation Tool Embedded Target for RH850 Available Learn more Contact