The 83PN128I is a programmable LVPECL synthesizer that can be used for frequency conversions. The device uses IDT's fourth generation FemtoClock® NG technology for optimal high clock frequency and low phase noise performance, combined with a low power consumption and high power supply noise rejection. Oscillator-level performance is maintained with IDT's 4th Generation FemtoClock® NG PLL technology, which delivers low rms phase jitter. The 83PN128I defaults to 161.132813MHz output using a 156.25MHz input with 2 select pins floating (pulled up with internal pullup resistors) but can also be set to 4 different frequency multiplier settings to support a wide variety of applications. The below table shows some of the more common application settings.

Features

  • Fourth Generation FemtoClock® NG technology
  • Footprint compatible with 5mm x 7mm differential oscillators
  • One differential LVPECL output pair
  • CLK, nCLK input pair can accept the following levels: HCSL, LVDS, LVPECL, LVHSTL and SSTL
  • Output frequency: 128.90MHz or 161.132813MHz
  • VCO range: 2.5GHz – 2.7GHz
  • Cycle-to-cycle jitter: 18ps (typical)
  • RMS phase jitter @ 128.90MHz, 12kHz – 20MHz: 0.53ps (typical)
  • Full 3.3V or 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete VFQFPN 10 I Yes Tray
Availability
Obsolete VFQFPN 10 I Yes Reel
Availability

Documentation

Title language Type Format File Size Date
Datasheets & Errata
ICS83PN128I Datasheet Datasheet PDF 404 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-831 The Crystal Load curve Application Note PDF 395 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-832 Timing Budget and Accuracy Application Note PDF 131 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 143 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-801 Crystal-High Drive Level Application Note PDF 202 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products Application Note PDF 108 KB
PCNs & PDNs
PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB
PCN# : W1308-01 Change of Passivation Thickness Product Change Notice PDF 941 KB
PDN# : CQ-16-04 QUARTER MARKET DECLINED PDN Product Discontinuation Notice PDF 560 KB
Other
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB