The 8413S08I is a PLL-based clock generator specifically designed for Cavium Networks SoC processors. This high performance device is optimized to generate the processor core reference clock, the PCI/PCI-X/PCIe bus clocks, the clocks for both the Gigabit Ethernet MAC and PHY and also the optional SGMII clock. The clock generator offers ultra low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN56xx series of processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The industrial temperature range of the 8413S08I supports tele- communication, networking, and storage requirements.

Features

  • Eight selectable 100MHz or 125MHz clocks for PCI Express™ and sRIO, HCSL interface levels
  • One 156.25MHz SGMII clock, LVPECL interface levels
  • Three LVCMOS/LVTTL outputs, 20Ω output impedance
  • Selectable external crystal or differential (single-ended) input source
  • Crystal oscillator interface designed for 25MHz, parallel resonant crystal
  • Differential CLK, nCLK input pair that can accept: LVPECL, LVDS, LVHSTL, HCSL input levels
  • Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels
  • Output supply voltage modes:
    VDD / VDDO
    3.3V/3.3V
    3.3V/2.5V
  • Full 3.3V output supply mode (HCSL)
  • PCI Express™ (2.5 Gb/s), Gen 2 (5 Gb/s), and Gen 3 (8 Gb/s) jitter compliant
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package​

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 56 I Yes Tray
Availability
Active VFQFPN 56 I Yes Reel
Availability

Documentation & Downloads

Title language Type Format File Size Date
Datasheets & Errata
ICS8413S08I Datasheet Datasheet PDF 788 KB
User Guides & Manuals
Timing Solutions for Cavium Processor Designs Guide PDF 810 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-831 The Crystal Load curve Application Note PDF 395 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-837 Overdriving the Crystal Interface Application Note PDF 133 KB
AN-832 Timing Budget and Accuracy Application Note PDF 131 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 143 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-801 Crystal-High Drive Level Application Note PDF 202 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products Application Note PDF 108 KB
PCNs & PDNs
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : A1807-01 Gold wire to Copper Wire Product Change Notice PDF 32 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB
Other
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB